III-Nitride Power Device Recess Gate for Normally-Off Operation
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Solution Overview
Problem
Conventional III-nitride power semiconductor devices are typically normally ON, requiring continuous gate voltage application to turn them OFF, which is energy-consuming and complicates drive circuitry, making it desirable to develop an enhancement mode (normally OFF) device.
Innovation Solution
A III-nitride power semiconductor device with a heterojunction structure including a P-type semiconductor layer grown epitaxially, a recess, and a gate structure that attracts electrons to restore a conductive channel along sloping sidewalls, allowing for voltage-controlled OFF state without continuous gate voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional HEMT is designed as a normally ON device, then the device structure is simple and easy to manufacture, but continuous gate voltage application is required to turn the device OFF, increasing energy consumption and complicating drive circuitry
Solution Approach 1:
The patent changes the physical parameters of the semiconductor layers by introducing a P-type AlGaN layer with specific doping concentrations and a graded Al composition profile. This parameter change creates a depletion region that blocks the 2DEG channel at zero gate voltage, enabling normally OFF operation without continuous power consumption
Solution Approach 2:
The patent introduces a vertical dimension to the device structure by creating a recess and placing the gate electrode in a depression. This dimensional change allows the gate to effectively control the 2DEG channel through electric field modulation, enabling enhancement mode operation
2Ease of operation
If a P-type doped layer is introduced to create a depletion region for normally OFF operation, then the device can operate as enhancement mode, but P-type implantation creates defects that become N-type, making it difficult to achieve enhancement type device
Solution Approach 1:
The patent replaces the mechanical implantation process with epitaxial growth to form the P-type AlGaN layer. This substitution eliminates the defect formation associated with ion implantation, as epitaxial growth allows for controlled in-situ doping without creating lattice damage or unwanted N-type regions
Solution Approach 2:
The patent uses a composite heterostructure consisting of multiple III-nitride layers with different compositions and doping types (N-type AlGaN, P-type AlGaN, undoped GaN). This composite material approach allows the P-type layer to be grown epitaxially with controlled doping, avoiding the defects associated with implantation while maintaining the desired electrical properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables a normally OFF operation with reduced energy consumption and simplified drive circuitry by using an epitaxially grown P-type layer and a gate structure that selectively forms a conductive channel, enhancing the device's control and efficiency.
Implementation Method 1
the heterojunction of the first semiconductor body and the second semiconductor body results in the formation of a carrier-rich conductive region usually referred to as a two dimensional electron gas or 2DEG
Implementation Method 2
The application of an appropriate voltage to the gate electrode causes the interruption of the 2DEG thereby turning the device OFF
Implementation Method 3
a second III-nitride semiconductor body, which may be composed of, for example, N-type AlGaN, disposed over the first semiconductor body
Implementation Method 4
a heterojunction body including a first portion, a second portion, and a third portion sloping at an angle between the first portion and the second
Data Source
AI summary
An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over at least a sidewall of the recess.