Recess Gate Fabrication with Planarized Conductive Layers

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Solution Overview

Problem

The existing recess gate fabrication method causes excessive damage to field oxide layers and height differences in the conductive layer, leading to deteriorated device characteristics such as leaning gates and reduced refresh characteristics in semiconductor devices.

Innovation Solution

A method involving the formation of a hard mask pattern over a substrate with field oxide layers, etching to create recesses, followed by planarizing a conductive layer to minimize damage and height differences, and forming a second conductive layer over the planarized surface, thereby reducing field oxide layer damage and height discrepancies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the oxide-based hard mask is removed using a wet cleaning process, then the mask is eliminated, but the field oxide layers are further damaged

Engineering Contradiction:

Improvemask removalVSAvoidfield oxide layer damage

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The upper hard mask layer is made of silicon nitride, which has similar chemical properties to the field oxide layers. This homogeneity in material composition allows the upper layer to be removed selectively without damaging the field oxide layers, as the removal process is designed to target silicon nitride specifically while leaving the oxide-based field oxide layers intact.

Inventive Principle:

Principle #33Homogeneity

2Reliability

If recesses are formed in the substrate to increase channel length, then refresh characteristic is improved, but height differences occur in the conductive layer causing seams in subsequent metal layers

Engineering Contradiction:

Improverefresh characteristicVSAvoidheight uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent fills the recesses with conductive material to create a raised conductive layer structure. This transforms the three-dimensional recess geometry into a planarized surface by adding material in the vertical dimension, thereby eliminating height differences while preserving the underlying recess structure that provides the refresh characteristic improvement.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves device characteristics by minimizing field oxide layer damage and eliminating height differences, enhancing the refresh characteristics and overall performance of semiconductor devices.

Implementation Method 1

etching a certain portion of an active region of a substrate such that a gate is formed over a recess

Methodology Applied

Scientific EffectEtching: Ablation

Implementation Method 2

planarizing a conductive layer to minimize damage and height differences

Methodology Applied

Scientific EffectPlanarization:

Data Source

PatentUS7575974B2Method for fabricating semiconductor device including recess gate

Publication Date: 2009.08.18 SK HYNIX INC

AI summary

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.