Recess Gate Semiconductor Device Asymmetrical Source Drain
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Solution Overview
Problem
Conventional semiconductor device manufacturing techniques face challenges with the short channel effect, spiking phenomenon, and increased parasitic series resistance due to the shortening of gate channel lengths and shallow source/drain areas, leading to degraded performance and reliability.
Innovation Solution
A method involving the formation of a recess gate with asymmetrical source/drain areas through inclined ion implantation and polysilicon spacers to enhance the thickness of the silicon layer and channel length, reducing parasitic series resistance and preventing electric field dispersion, while controlling the threshold voltage and punch-through phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate channel length is shortened to achieve high integration, then the device density increases, but the short channel effect occurs causing threshold voltage degradation
Solution Approach 1:
The patent transitions from a planar gate structure to a recess gate structure by etching a groove into the semiconductor substrate. This dimensional change allows the gate to extend vertically into the substrate, increasing the effective gate channel length without increasing the planar footprint, thereby maintaining high integration density while improving gate control
Solution Approach 2:
The patent performs preliminary ion implantation to form LDD (lightly doped drain) regions and adjusts the threshold voltage before forming the gate structure. This preliminary action prepares the semiconductor substrate to compensate for short channel effects that will occur with the shortened gate channel length
2Reliability
If the source/drain area depth is increased to reduce parasitic series resistance, then the resistance decreases, but the spiking phenomenon occurs due to silicon layer reaction with metallic materials
Solution Approach 1:
The patent applies different doping concentrations to different regions: lightly doped LDD regions adjacent to the gate and heavily doped source/drain regions further away. This local quality variation allows the silicon layer thickness to be effectively increased in the LDD region to reduce parasitic resistance while preventing spiking in the heavily doped source/drain areas
Solution Approach 2:
The LDD region acts as an intermediary between the gate and the source/drain areas. It provides a transition zone where the doping concentration gradually changes, preventing direct contact between the silicon layer and metallic materials that would cause spiking, while still reducing parasitic series resistance
3Reliability
If the silicon layer thickness in the junction area is increased to reduce parasitic series resistance, then the resistance decreases, but the manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions into the LDD region formation step: threshold voltage adjustment, parasitic resistance reduction, and spiking prevention are all achieved through the ion implantation process that creates the LDD regions. This merging reduces the need for separate manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic series resistance, restricts the short channel effect, and improves current characteristics by enhancing the thickness of the silicon layer and channel length, thereby improving the reliability and operational efficiency of semiconductor devices.
Implementation Method 1
forming an impurity doping area in a source area of the semiconductor substrate adjacent to the spacer by primarily implanting first conducive impurities through an inclined ion implantation scheme
Data Source
AI summary
A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.