Recess Gate Transistor Channel Length Extension

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Solution Overview

Problem

Recess Channel Array Transistors and Buried Channel Array Transistors face challenges with short channel effects, such as source to drain leakage and reduced carrier mobility, due to their short conduction channels, which are not effectively addressed by existing semiconductor technologies.

Innovation Solution

A method of forming semiconductor devices with recess gates involves creating trenches, depositing insulating and conductive layers, and using specific materials like silicon nitride and metal conductive materials to enhance transistor drive characteristics while minimizing metal contamination and stress damage, with precise control over gate dimensions and etch selectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If planar transistors are used, then manufacturing is simpler, but channel length is short causing short channel effects

Engineering Contradiction:
Improvetransistor fabrication simplicityVSAvoidchannel length
Core Design Contradiction:
Ease of manufactureVSLength of moving object

Solution Approach 1:

The patent transitions from planar (2D) transistor structure to recess gate structure by etching trenches into the substrate, adding a vertical dimension to the channel formation. This allows the channel to extend both horizontally and vertically, achieving longer effective channel length while maintaining compact planar footprint for simple integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The channel region is segmented into multiple portions by creating recesses (trenches) within the substrate. The channel is divided into sections separated by insulating layers and conductive patterns, allowing the total channel length to be extended through vertical segmentation rather than a single long horizontal channel.

Inventive Principle:
Principle #1Segmentation

2Reliability

If channel length is increased to reduce short channel effects, then leakage decreases, but drive current is reduced

Engineering Contradiction:
Improveleakage controlVSAvoiddrive current
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

Different regions of the channel have different properties: the recessed portions contain insulating layers for better leakage control, while the raised portions maintain shorter channel characteristics for higher drive current. The conductive patterns at the bottom of trenches provide localized field control to optimize both leakage and drive current in different spatial zones.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The channel structure combines multiple materials including semiconductor substrate, insulating materials (silicon oxide, silicon nitride), and conductive materials (metal patterns, polysilicon). This composite structure allows simultaneous optimization of leakage control (through insulating regions) and drive current (through conductive regions and optimized semiconductor portions).

Inventive Principle:
Principle #40Composite materials

3Reliability

If recess gate structure is used, then channel length increases and leakage decreases, but manufacturing complexity increases

Engineering Contradiction:
Improveshort channel effect controlVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Hard mask layers (silicon nitride, polysilicon) are introduced as intermediary structures to define and protect the trench regions during fabrication. These intermediary layers enable precise pattern transfer and etching control, making the complex recess gate fabrication process manageable through standardized photolithography and etching steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The hard mask layers are formed and patterned before the actual trench etching and channel formation steps. This preliminary patterning establishes the precise geometry of the recesses, ensuring accurate channel length and width control throughout subsequent fabrication steps, thereby managing complexity through pre-planned structure definition.

Inventive Principle:
Principle #10Preliminary action

4Area of stationary object

If gate-to-gate dimension is reduced for ultra-compact integration, then device density increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvegate spacingVSAvoiddimensional control
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The hard mask patterns are used as templates or copies to define the trench positions and dimensions. The photolithographically patterned masks are replicated through etching processes, ensuring consistent gate-to-gate spacing across the wafer. This copying approach enables precise dimensional control even at reduced gate pitch by relying on well-established lithography resolution limits.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach improves transistor drive characteristics and reduces leakage effects by extending channel lengths, enhancing carrier mobility and threshold voltage control, suitable for ultra-compact integration in semiconductor memory devices.

Implementation Method 1

forming a conductive layer on the second insulating layer; removing the conductive layer from the upper portion of the trenches, with a conductive layer pattern remaining at the bottom portion of the trenches

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing a buffer layer on the conductive layer patterns and the trench walls

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS8889539B2Recess gate transistor
Publication Date: 2014.11.18 SAMSUNG ELECTRONICS CO LTD
  • US8889539B2 patent drawing
  • US8889539B2 patent drawing
  • US8889539B2 patent drawing

AI summary

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.