Recess Spacer Etch for Independent Transistor Group Optimization
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Solution Overview
Problem
Conventional semiconductor processes lack the ability to independently control spacer widths for different transistor groups, limiting the optimization of transistor performance in semiconductor devices.
Innovation Solution
A method using a sacrificial photoresist layer to delay the onset of etching in specific transistor regions, allowing for the formation of spacer structures with different dimensions, enabling independent optimization of transistor performance by varying the photoresist thickness and etching processes across different transistor regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single spacer width is used for all transistor devices in a circuit, then the manufacturing process is simplified, but the optimization of transistor performance is limited
Solution Approach 1:
The patent divides the transistor circuit into multiple groups (first transistor group and second transistor group) with different spacer width requirements. By applying selective photoresist masking to specific regions, each transistor group can have independently optimized spacer widths. This segmentation allows different spacer widths (e.g., narrower spacers for high-performance transistors, wider spacers for low-power transistors) without complicating the overall manufacturing process.
Solution Approach 2:
The patent implements local quality by applying different spacer widths to different transistor groups based on their specific performance requirements. The selective photoresist masking enables certain regions to have narrower spacers for optimized drive current while other regions have wider spacers for reduced leakage or improved stability. This local differentiation optimizes overall circuit performance without requiring complete process redesign.
2Reliability
If independent control of spacer widths for different transistor groups is implemented, then transistor performance optimization is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by depositing a uniform photoresist layer across the entire substrate before selective removal. This preliminary step establishes a baseline masking layer that protects all transistor groups initially. Subsequently, selective etching or selective photoresist removal in specific regions creates the desired differential spacer widths. This approach avoids the need for multiple separate masking and deposition steps, thereby reducing overall process complexity while achieving independent spacer width control.
Solution Approach 2:
The photoresist layer serves as an intermediary material that enables differential spacer width formation. By selectively removing or retaining photoresist in different transistor regions, the patent uses this intermediary to control the etching process and achieve the desired spacer width variations. This intermediary approach simplifies the process compared to attempting direct spacer deposition with different widths, as it leverages the photoresist's ease of selective application and removal.
3Reliability
If narrower spacer widths are used to move source/drain junctions closer to the channel, then transistor drive current is improved, but parasitic source/drain resistance control becomes more difficult
Solution Approach 1:
The patent applies local quality by implementing different spacer widths in different transistor groups based on their specific performance requirements. High-performance transistors requiring maximum drive current receive narrower spacers that position source/drain junctions closer to the channel, maximizing overlap capacitance and drive strength. Meanwhile, other transistor groups receive wider spacers that provide better parasitic resistance control through increased spacing. This localized differentiation allows each transistor group to be optimized for its specific function without compromising overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for independent optimization of spacer widths and recess depths in multiple transistor groups, enhancing transistor performance and simplifying the manufacturing process by reducing the complexity of achieving multiple spacer widths.
Implementation Method 1
A first layer of photoresist is disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered. The structure is then subjected to an etch which etches the first layer of photoresist and a portion of the first and second sets of spacer structures. The presence of the first layer of photoresist has the effect of delaying the onset of etching of the second set of spacer structures relative to the first set of spacer structures.
Data Source
AI summary
A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively. A first layer of photoresist (231) is disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered. The structure is then subjected to an etch which etches the first layer of photoresist and a portion of the first and second sets of spacer structures.