Recessing STI to Increase Fin Height in FinFET Fabrication
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Solution Overview
Problem
In FinFET fabrication, existing processes face challenges in increasing the height of semiconductor fins while maintaining the integrity of the STI regions and preventing electrical shorting, which limits the drive current and channel width of FinFETs.
Innovation Solution
The process involves recessing STI regions after forming source and drain regions, using a dielectric mask layer to control etching and prevent undercutting, allowing for increased fin height without compromising the structure and reducing the risk of electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If STI regions are recessed to increase fin height, then drive current and channel width are improved, but structural integrity of STI regions deteriorates and electrical shorting risk increases
Solution Approach 1:
A dielectric mask layer is formed on the STI regions before the recessing process. This preliminary protective action allows the STI to be recessed to the required depth for increased fin height while the mask layer prevents structural damage and electrical shorting during etching, enabling both improved drive current and maintained structural integrity
Solution Approach 2:
The dielectric mask layer serves as an intermediary protective element between the etching process and the STI regions. It allows controlled recessing to increase fin height for higher drive current while preventing undercutting and electrical shorting that would otherwise occur, thus resolving the contradiction between productivity improvement and reliability maintenance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective channel width and saturation current of FinFETs by increasing fin height, improving drive current while maintaining structural integrity and preventing electrical shorting.
Implementation Method 1
The process involves recessing STI regions after forming source and drain regions, using a dielectric mask layer to control etching and prevent undercutting
Data Source
AI summary
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.