Stacked Chip Package With Recess Substrate For Miniaturization
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Solution Overview
Problem
The existing stacked chip packages face challenges in reducing size due to external conducting structures, which increase the overall package size, making it difficult to further miniaturize them.
Innovation Solution
A stacked chip package design featuring a first substrate with recesses and redistribution layers that extend onto the bottom of these recesses, allowing bonding wires to connect with a second substrate, thereby reducing the package size by eliminating the need for external conducting structures that protrude from the top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external conducting structures are used to connect chip package to packaging component, then electrical connectivity is achieved, but the overall package size increases
Solution Approach 1:
The patent transitions from planar external conducting structures to three-dimensional internal conducting structures by forming recesses in the substrate and extending redistribution layers into these recesses. This vertical integration allows bonding wires to connect substrates without requiring external conducting structures, thereby reducing package size while maintaining electrical connectivity.
Solution Approach 2:
The redistribution layers are nested within the recesses of the substrate, creating a compact internal structure. This nesting approach embeds the conducting structures within the substrate volume rather than extending them externally, effectively reducing the overall package footprint while preserving electrical connection functionality.
2Adaptability or versatility
If bonding wires are extended onto second substrate through recesses, then layout flexibility and signal transmission speed are enhanced, but manufacturing complexity increases
Solution Approach 1:
The substrate is segmented by forming recesses that create distinct regions for different functions. The redistribution layers are segmented to extend into specific recesses, allowing independent optimization of different connection paths. This segmentation enables flexible layout design while organizing the manufacturing process into manageable stages.
Solution Approach 2:
The recesses are formed in the substrate before the redistribution layers are deposited. This preliminary structuring of the substrate creates pre-defined pathways that guide subsequent material deposition and wire bonding processes, simplifying the overall manufacturing sequence despite the increased structural complexity.
Data Source
AI summary
A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.