Source/Drain Recess Volume Trim for Strained Channel MOSFETs
Solution Overview
Problem
In semiconductor manufacturing, strained source and drain regions in MOSFETs face challenges due to dislocations and topology distortions caused by germanium-containing materials like SiGe, which degrade device performance, especially at advanced technology nodes.
Innovation Solution
A method involving an anisotropic etch process with a boron-containing dopant to form a flat bottom surface in the recesses, followed by deposition of stress-inducing materials like SiGe or SiC to create a strained channel, enhancing carrier mobility while minimizing dislocations and distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If germanium-containing materials like SiGe are used to create strained source and drain regions, then carrier mobility is enhanced, but dislocations and topology distortions occur that degrade device performance
Solution Approach 1:
The patent applies local quality by creating a graded germanium composition profile where the germanium concentration varies spatially within the source and drain regions. The composition is adjusted locally to induce strain in the channel region while maintaining structural integrity at the interfaces, thereby enhancing carrier mobility without generating excessive dislocations that would degrade device reliability.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the germanium composition gradient and recess depth parameters. By optimizing these parameters, the patent achieves the desired strain effect for improved carrier mobility while controlling the formation of dislocations and topology distortions to maintain device performance.
2Speed
If strained source and drain regions are formed to enhance carrier mobility, then MOSFET performance is improved, but layout dependence increases at advanced technology nodes
Solution Approach 1:
The patent applies segmentation by dividing the source and drain structures into distinct regions with different germanium compositions. This segmentation allows independent optimization of each region to achieve uniform strain distribution that reduces layout dependence while maintaining enhanced carrier mobility across different device geometries at advanced technology nodes.
3Speed
If recesses are etched to accommodate stress-inducing materials, then strained channel is produced, but manufacturing precision is challenged by anisotropic etching requirements
Solution Approach 1:
The patent applies preliminary action by performing doping and material deposition steps before the final recess etching. This sequence allows the stress-inducing materials to be in place during recess formation, enabling better control of the etching process and reducing the precision requirements for creating the final recess geometry while still achieving the desired strained channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances carrier mobility by producing a strained channel with reduced dislocations and topology distortions, improving MOSFET performance, particularly at advanced technology nodes.
Implementation Method 1
Anisotropic etching is then performed on the substrate. The etch stop layer resists the anisotropic etching such that the recesses comprise substantially flat bottom surfaces.
Implementation Method 2
an implantation process to form an etch stop layer along a bottom surface of the recesses
Implementation Method 3
Strained-layer epitaxy to produce a strained channel with enhanced carrier mobility within a metal-oxide semiconductor field-effect transistor (MOSFET) is achieved through the formation of strained source and drain regions within the MOSFET.
Data Source
AI summary
Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.