Recessed Access Device Array with Insulated Islands
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Solution Overview
Problem
In the fabrication of memory and other circuitry, the challenge lies in reducing component size and spacing to minimize parasitic capacitance and cross-talk between adjacent components, while maintaining the non-volatile nature of ferroelectric capacitors and the functionality of recessed access devices.
Innovation Solution
The implementation of an array of recessed access devices and memory cells, where each memory cell comprises a capacitor and a transistor, with a substrate structure featuring semiconductive islands surrounded by insulating material, and wordlines and digitlines that intersect at specific angles to reduce noise and parasitic capacitance, and a method of fabrication involving trench formation and doping to optimize the layout and operation of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If component size and spacing are reduced to minimize parasitic capacitance and cross-talk, then manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D component layout to 3D vertical stacking architecture. Memory cells are arranged in multiple tiers with through-silicon vias (TSVs) enabling vertical interconnects between layers. This dimensional change allows components to be spaced closer in the vertical dimension while maintaining adequate horizontal spacing, thereby reducing parasitic capacitance and cross-talk without compromising manufacturing precision.
Solution Approach 2:
The patent implements nested structures where capacitor electrodes are embedded within the substrate, access devices are formed in trenches, and multiple functional layers are integrated within each other. The capacitor lower electrode is formed in a first region, the upper electrode in a second region, with insulating and conductive layers nested between them. This nesting allows compact component placement while maintaining electrical isolation and reducing parasitic effects.
2Area of moving object
If component size is reduced, then area is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory cell structure into segmented functional regions: capacitor lower electrode region, capacitor upper electrode region, access device region, and interconnect regions. Each region is formed through dedicated processing steps including selective etching, deposition, and doping. This segmentation allows independent optimization of each component while maintaining compact overall area, though it increases fabrication process complexity.
Solution Approach 2:
The patent employs universal structures that serve multiple functions: the substrate serves as both mechanical support and electrical interconnect layer; TSVs provide both structural alignment and electrical connectivity between tiers; the gate insulator layer serves as both electrical isolation and part of the capacitor dielectric. This multi-functionality reduces the number of separate components needed, thereby reducing area despite increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the creation of smaller, closer-spaced components with reduced parasitic capacitance and cross-talk, while maintaining the non-volatile characteristics of ferroelectric capacitors and enhancing the performance of recessed access devices, thereby improving the efficiency and reliability of memory and other circuitry.
Implementation Method 1
A gate insulator is between the gate electrode and the channel region
Implementation Method 2
One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states
Implementation Method 3
The individual transistors comprise a pair of source/drain regions on opposite sides of the individual gate lines in the individual islands
Data Source
AI summary
An array of recessed access devices comprises islands comprising semiconductive material surrounded by insulating material. The insulating material has a bottom adjacent individual of the islands. Rows of transistor gate lines individually cross multiple of the islands within the semiconductive material and cross within the insulating material between the individual islands. Individual of the gate lines are operatively adjacent a channel region of individual of the transistors within the individual islands and interconnect the transistors in that row. The individual transistors comprise a pair of source/drain regions on opposite sides of the individual gate lines in the individual islands. A lower portion of the individual islands proximate individual of the bottoms of the insulating material has less horizontal area than an uppermost portion of the individual islands. Additional embodiments are disclosed.