Recessed Access Device Transistor With Neck And Rounded Portion
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Solution Overview
Problem
Conventional semiconductor transistors face challenges with the 'short channel effect' and increased gate resistance due to miniaturization, leading to unintended transistor activation and high gate-induced drain leakage (GIDL) current, particularly in recessed access device (RAD) transistors with deep metallurgical junctions.
Innovation Solution
A method for forming a recessed access device transistor with a shallow metallurgical junction and optimized channel length, involving anisotropic and isotropic etching techniques to create a neck and rounded portion structure, reducing vertical overlap between the gate and active area, and using conformal spacer materials to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to overcome the short channel effect, then transistor activation control improves, but the lateral space required increases
Solution Approach 1:
The patent transitions from a conventional planar channel to a three-dimensional recessed channel structure. The channel is formed extending downward into the substrate from the surface, utilizing the vertical dimension to increase channel length while maintaining a compact lateral footprint. This dimensional transition allows the channel to provide sufficient length for proper transistor control without occupying excessive horizontal space on the chip.
Solution Approach 2:
The recessed channel structure is nested within the substrate, with the channel forming a trench-like structure that extends vertically into the material. The gate structure is then formed over and around this recessed channel, creating a nested configuration where the functional elements are arranged in multiple levels rather than a single plane, thereby increasing channel length without proportionally increasing lateral dimensions.
2Productivity
If the gate cross sectional area is decreased to reduce gate resistance, then gate resistance increases, but miniaturization continues
Solution Approach 1:
The gate structure extends vertically along the recessed channel, utilizing the vertical dimension to increase the gate's effective cross-sectional area for current conduction. This vertical extension provides additional parallel conduction paths that reduce gate resistance without requiring an increase in lateral gate dimensions, thus maintaining miniaturization while improving electrical performance.
Solution Approach 2:
The gate structure comprises multiple material layers including conductive materials arranged in a composite configuration. This multi-layer composite structure optimizes both the electrical conductivity (reducing resistance) and the spatial efficiency (maintaining miniaturization) by strategically selecting and arranging materials with different electrical properties within the constrained gate volume.
3Length of stationary object
If the metallurgical junction depth is increased in RAD transistors, then channel length increases, but gate-induced drain leakage current increases
Solution Approach 1:
The patent implements non-uniform doping concentrations along the channel length, with lighter doping near the gate region and heavier doping toward the drain region. This localized variation in dopant concentration optimizes the electrical characteristics by reducing gate-induced drain leakage in the critical region near the gate while maintaining sufficient channel length for proper transistor control elsewhere in the structure.
Solution Approach 2:
The patent employs graded doping profiles and varies dopant concentrations at different positions along the channel and in different regions of the substrate. By changing the doping parameters (concentration, depth, distribution) in specific zones, the invention optimizes the balance between channel length and leakage current, creating regions with tailored electrical properties that mitigate GIDL while maintaining channel functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced gate-induced drain leakage and decreased short channel effects, improving transistor functionality and operational efficiency by maintaining a longer channel length without increasing lateral space, thus addressing the limitations of conventional RAD transistors.
Implementation Method 1
An anisotropic etch is performed on the FIG. 1 structure to form the trench 20 within the wafer 10
Implementation Method 2
A blanket spacer material 50, for example silicon nitride, is formed over the structure of FIG. 4
Data Source
AI summary
A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.