Recessed Active Trench Transistors for Drive Current
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Solution Overview
Problem
Current methods for fabricating integrated circuits struggle to increase drive current in wide transistors without a proportional increase in leakage current, limiting the performance of advanced microelectronic devices like SRAM and CMOS.
Innovation Solution
The method involves forming recessed active trenches in the substrate to effectively increase the transistor width without expanding the active area, using a combination of etching, oxidation, and nitride layer processing to create a nonplanar active area that enhances drive current while maintaining constant leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width of transistors is increased to increase drive current, then the drive current (ION) increases, but the leakage current (IOFF) increases proportionally
Solution Approach 1:
The patent introduces vertical dimension by etching recesses into the active area, transforming a 2D planar structure into a 3D non-planar structure. This allows the effective gate width to extend vertically into the substrate, increasing drive current without expanding the horizontal footprint, thereby avoiding proportional increase in leakage current.
Solution Approach 2:
The recessed active areas are nested within the planar active area, creating a multi-level structure where vertical recesses are embedded in the horizontal plane. This nesting approach allows additional transistor width to be packed within the same footprint, increasing drive current while maintaining controlled leakage characteristics.
2Power
If the transistor width is increased to increase drive current, then the drive current (ION) increases, but the device footprint increases
Solution Approach 1:
The patent utilizes the vertical dimension by etching recesses into the substrate, allowing the effective gate width to extend downward. This transforms the transistor structure from a purely 2D planar layout to a 3D non-planar structure, enabling increased drive current within the same horizontal footprint.
Solution Approach 2:
The active area is segmented into multiple recessed regions within the planar surface. Each recess contributes additional effective gate width, and the segmented structure allows the total drive current to be summed from multiple vertical segments without increasing the overall device footprint.
3Power
If recessed active trenches are formed to increase effective gate width, then the drive current (ION) increases, but the manufacturing complexity increases
Solution Approach 1:
The recesses are formed in the active area before the transistor fabrication process begins. This preliminary structuring of the substrate prepares the non-planar active areas in advance, allowing subsequent standard CMOS processing steps to proceed without significant modification, thereby limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant increase in drive current (up to 100% higher) with minimal area increase, making it suitable for wide transistor applications without increasing leakage current, thus improving the performance of logic and analog structures.
Implementation Method 1
The oxide trench is etched into the silicon substrate utilizing, for example, reactive ion etching (RIE)
Implementation Method 2
followed by employing a thermal oxidation process to line the trench walls with a thin layer of oxide
Implementation Method 3
The structure is subsequently chemically mechanically polished (CMP) to create a planar STI structure
Data Source
AI summary
A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.