Recessed Wafer Alignment Marks That Withstand CMP Planarization
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Solution Overview
Problem
Chemical-mechanical polishing (CMP) processes can damage alignment marks on semiconductor wafers, compromising their integrity and accuracy, which is crucial for precise layer alignment in photolithography and wafer fabrication.
Innovation Solution
The formation of alignment marks with recesses etched into the wafer surface and filled with conformal materials like silicon oxide or nitride, which are designed to withstand CMP procedures without damage, ensuring the marks' integrity and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional alignment marks are used on wafer surface, then alignment function is provided, but CMP process damages the alignment marks
Solution Approach 1:
The patent applies preliminary action by forming recesses in the wafer surface before depositing the alignment mark material. This pre-prepared structure allows the alignment marks to be embedded in protected recesses, preventing CMP damage before the polishing process begins. The recesses are formed and filled with protective material in advance, so when CMP is performed later, the alignment marks are already shielded from direct exposure to the polishing slurry.
Solution Approach 2:
The patent uses an intermediary material (such as silicon oxide or silicon nitride) that is deposited to fill the recesses and form the alignment marks. This intermediary material serves as a protective layer that withstands CMP processing while still allowing the alignment function to be performed. The intermediary material acts as a mediator between the vulnerable alignment mark structure and the damaging CMP process, enabling the marks to survive the polishing procedure intact.
2Reliability
If alignment marks are made robust to withstand CMP, then CMP damage is prevented, but manufacturing complexity increases
Solution Approach 1:
The patent segments the alignment mark structure into distinct components: recesses formed in the wafer surface, intermediary material filling the recesses, and alignment mark patterns formed on top. This segmentation allows each component to be optimized independently - the recesses provide structural protection, the intermediary material provides CMP resistance, and the alignment mark patterns provide the alignment function. By dividing the structure into functional segments, the overall complexity is managed while achieving durability.
Solution Approach 2:
The patent applies local quality by creating recesses only in specific locations where alignment marks are needed, rather than modifying the entire wafer surface. The protective intermediary material is deposited selectively to fill these localized recesses. This approach provides enhanced protection and durability precisely where required for alignment marks, while leaving the rest of the wafer structure unchanged, thereby minimizing overall manufacturing complexity.
Data Source
AI summary
The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.