Recessed Bonding Pad for 3D Semiconductor Interconnects
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Solution Overview
Problem
Conventional wafer-level 3D bonding techniques face challenges such as alignment accuracy, bonding strength, thinning uniformity, and the need for flux in forming stacked structures, which affect the reliability and efficiency of semiconductor packaging.
Innovation Solution
A semiconductor structure featuring a protrusion on the front side and a recess on the backside, with specific metal layer configurations and oxidation properties, and a method for manufacturing this structure that includes forming through via holes, sidewall structures, and filling patterns to enable intermetallic bonding without the use of flux.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional protruding-type electrode structure is used, then bonding can be achieved, but joining defects occur and bonding reliability decreases
Solution Approach 1:
The patent inverts the conventional protruding electrode structure by making the bonding interface recessed rather than protruding. The bonding pad is formed in a recess on the chip surface, and the electrode on the substrate fits into this recess, creating an inverted configuration that eliminates joining defects and improves bonding reliability.
Solution Approach 2:
The electrode on the substrate is nested within the recess formed in the chip's bonding pad area. This nesting configuration allows the electrode to be surrounded and protected by the chip structure, eliminating exposure to external contaminants and mechanical damage that cause joining defects.
2Length of stationary object
If conventional protruding electrode structure is used, then bonding is achieved, but stack height increases due to protruding electrode portion
Solution Approach 1:
By inverting the electrode structure from protruding to recessed, the patent eliminates the height increase caused by protruding electrodes. The bonding interface is now below the chip surface level, allowing the stack to be more compact and reducing overall stack height.
3Manufacturing precision
If conventional wafer-level 3D bonding is used, then higher density is achieved, but alignment accuracy is affected by bow and stress build-up
Solution Approach 1:
The patent applies local quality by creating a recessed bonding interface that locally accommodates and distributes stress. The recess structure provides a stress-relief zone that prevents bow and stress build-up from affecting overall alignment accuracy during wafer-level bonding.
4Ease of manufacture
If conventional bonding process is used, then bonding is achieved, but flux is required which complicates the process
Solution Approach 1:
The patent extracts and eliminates the need for flux from the bonding process by using the recessed bonding structure that enables direct metal-to-metal contact and intermetallic bonding without requiring flux as a medium.
Solution Approach 2:
The recessed bonding structure enables self-aligned bonding where the electrode automatically fits into the recess, creating strong intermetallic bonds without requiring external flux assistance. The structure itself provides the bonding mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves alignment, bonding strength, and reduces the need for flux, resulting in a more reliable and efficient semiconductor packaging process with enhanced intermetallic bonding, which anchors semiconductor structures securely.
Implementation Method 1
an extent of oxidation of the first outer metal layer may be greater than an extent of oxidation of the second metal layer
Implementation Method 2
enhanced intermetallic bonding, which anchors semiconductor structures securely
Data Source
AI summary
Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.