Recessed Bottom Contact for MTJ Alignment
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving a magnetic resistance element with improved characteristics, such as increased integration density and reliability, while maintaining the flatness of the tunnel barrier layer to prevent Neel coupling and degradation of the MTJ structure, which is difficult due to the need for a thicker bottom layer for patterning and planarization.
Innovation Solution
The solution involves forming a semiconductor memory device with a recess in the interlayer dielectric layer that has a wine glass shape, allowing the bottom layer to fill the recess and protrude out, ensuring the MTJ structure's flatness and alignment, and using a conductive material for the bottom layer that is different from the bottom contact, facilitating easier planarization and alignment of the MTJ structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bottom layer is made thicker to improve patterning alignment, then the alignment of the MTJ structure is improved, but the fabrication complexity increases due to additional recess formation steps
Solution Approach 1:
The recess structure serves multiple functions: it provides the necessary vertical space for the thick bottom layer, establishes the horizontal alignment reference for the MTJ structure, and maintains the coplanar surface for subsequent layer deposition. By combining these functions into a single structural feature, the patent avoids adding excessive fabrication complexity while achieving improved alignment.
2Ease of manufacture
If the bottom layer protrudes above the interlayer dielectric layer to facilitate planarization, then the planarization process is simplified, but the flatness of the tunnel barrier layer deteriorates
Solution Approach 1:
Instead of allowing the bottom layer to protrude above the interlayer dielectric layer as in conventional approaches, the patent inverts the approach by creating a recess in the interlayer dielectric layer that accommodates the bottom layer. This inversion allows the bottom layer to achieve sufficient thickness without compromising the flatness of the upper surface where the tunnel barrier layer will be formed.
Data Source
AI summary
An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.