Recessed Capping Layer in Thin Film Transistor Array Panel
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Solution Overview
Problem
The characteristics of thin film transistors in flat panel displays deteriorate due to reactions between metal wiring layers and other layers during the manufacturing process, leading to reduced charge mobility and poor etching profiles, especially when a silicon oxide passivation layer is formed.
Innovation Solution
A thin film transistor array panel design that includes a capping layer with metal oxide, such as indium-zinc oxide, where the end of the capping layer is inwardly recessed relative to the data wire layer, and a method of manufacturing that uses a series of photosensitive film patterns to control the etching profile, including dry etching with argon gas, to prevent damage and improve transistor quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capping layer including metal oxide is formed between the main wiring layer and the passivation layer to prevent oxidation, then the main wiring layer is protected from oxidation and charge mobility is maintained, but it is difficult to control the etching profile due to difference in etching speeds between the main wiring layer and the capping layer
Solution Approach 1:
The patent applies local quality by creating a recessed portion in the capping layer at the edge region, while maintaining the capping layer's protective function in the central region. This localized structural modification allows different etching behaviors in different regions: the recessed edge region enables proper etching profile control, while the covered central region continues to protect the main wiring layer from oxidation, thus maintaining charge mobility.
2Reliability
If the capping layer completely covers the data wire layer to protect it, then the data wire layer is protected from damage, but the etching profile cannot be controlled and product quality deteriorates in subsequent processing
Solution Approach 1:
The patent segments the capping layer's coverage by creating a recessed portion at the edge region, separating it from the fully covered central region. This segmentation allows the capping layer to fulfill its protective function in the central region while enabling etching profile control in the recessed edge region, thus resolving the contradiction between protection and etching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents damage during subsequent processing and enhances the quality of the thin film transistor array panel by maintaining the integrity of the capping layer and data wire layer, reducing the risk of passivation layer cracking and improving transistor characteristics.
Implementation Method 1
charge mobility may be reduced due to oxidation of the main wiring layer material
Implementation Method 2
a method of manufacturing that uses a series of photosensitive film patterns to control the etching profile, including dry etching with argon gas
Data Source
AI summary
A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.