Recessed Channel Array Transistors With Non-Uniform Gate Oxide
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Solution Overview
Problem
In recessed channel array transistors, the short channel effect due to small device size leads to gate-induced leakage current and malfunction, primarily caused by the large area of source/drain regions confronting the gate electrode and concentrated electric fields at the gate edge, which acts as a parasitic transistor.
Innovation Solution
A recessed channel array transistor design with a gate oxide layer having varying thicknesses, where the thickness on the side edges is greater than 70% of the thickness on the side surface, and a plasma oxidation process is used to form the gate oxide layer, reducing sharp ends and concentrating the electric field, thereby minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is reduced to deep sub-micron to improve operational speed and current drive capacity, then the operational speed and current drive capacity are improved, but short channel effect is generated causing gate malfunction and leakage current
Solution Approach 1:
The patent introduces a recessed channel structure that extends vertically into the substrate, adding a depth dimension to the channel. This three-dimensional configuration allows the channel length to be effectively increased along the vertical axis while maintaining a short horizontal footprint, thus achieving deep sub-micron device dimensions without suffering from short channel effects.
Solution Approach 2:
The gate oxide layer is designed with non-uniform thickness, being thicker at the edges of the recessed channel and thinner at the center. This local variation in oxide thickness is specifically engineered to modulate the electric field distribution, preventing field concentration at the gate edges that would otherwise create parasitic transistors and leakage paths.
2Power
If the source/drain regions have large area confronting the gate electrode to improve current drive, then the current drive capacity is improved, but gate induced leakage current increases
Solution Approach 1:
The gate oxide layer thickness is locally optimized with thicker regions at the source/drain edges under the gate and thinner regions in the channel center. This spatially varying thickness profile allows adequate spacing to reduce leakage while maintaining strong field control in the channel region for high current drive.
3Force
If the gate electrode edge functions as parasitic transistor to concentrate electric field, then the electric field concentration occurs, but double bump turn-on is generated causing malfunction
Solution Approach 1:
The gate oxide layer is designed with non-uniform thickness, being thicker at the edges of the recessed channel and thinner at the center. This local variation in oxide thickness is specifically engineered to modulate the electric field distribution, preventing field concentration at the gate edges that would otherwise create parasitic transistors and leakage paths.
Solution Approach 2:
The recessed channel structure features rounded corners and curved surfaces rather than sharp edges. This curvature eliminates the geometric field concentration points that would act as parasitic transistor gates, ensuring uniform electric field distribution and preventing double bump turn-on behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces gate-induced leakage current and improves operational characteristics by distributing the electric field more evenly, enhancing the operational speed and reliability of the transistor.
Implementation Method 1
a plasma oxidation process is used to form the gate oxide layer
Data Source
AI summary
A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.