Recessed Channel Transistor Structure for Leakage Field Control
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in scaling down multi-gate and nanowire transistors, where there is a trade-off between feature size and spacing, leading to increased leakage in narrow bandgap devices, and the need for high bandwidth computing requires innovative solutions for gate field modulation and power delivery.
Innovation Solution
The implementation of recessed channel transistors with gate field modulation using oxide thickness modulation and backside power delivery, which reduces gate-induced leakage and enhances performance by integrating recessed channel devices with nanowire or fin-based layers, and employing insulating materials to reduce fringing fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase device density, then the number of devices per chip increases, but leakage current increases and short channel control deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire channels extending vertically through the substrate. This dimensional change allows the channel to surround the gate electrode completely (gate-all-around configuration), providing superior electrostatic control and reducing leakage current while maintaining small footprint for high device density.
Solution Approach 2:
The gate electrode is positioned inside and surrounded by the nanowire channel, creating a nested configuration where the gate is enclosed within the channel structure. This gate-all-around geometry enables the gate to control the channel from all directions, improving short channel control and reducing leakage without increasing device area.
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but gate field control and mobility improvement are compromised
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the nanowire channel and the bulk silicon substrate. This insulating layer electrically isolates the channel from the substrate, enabling effective gate control and preventing substrate-induced leakage, while still allowing the use of cost-effective bulk silicon substrates rather than requiring silicon-on-insulator wafers.
3Manufacturing precision
If lithographic processes are used to pattern small features, then feature size decreases, but spacing between features must increase, reducing device density
Solution Approach 1:
The patent utilizes vertical nanowire channels extending through the substrate thickness, allowing devices to be packed closely in the planar direction without increasing spacing requirements. The third-dimensional vertical channel structure enables high device density while maintaining small lithographic feature sizes for precise patterning.
Data Source
AI summary
Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.