Recessed Channel Nonvolatile Memory Array Scalability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nonvolatile nitride memory cell structures face issues with scalability, high power program and erase operations, and high sheet resistance due to their planar structure.
Innovation Solution
The introduction of a nonvolatile memory cell array with a recessed channel region interface, where the channel region is formed into a substrate, and dielectric structures are placed between the charge storage structure and the gate voltage source, enabling improved scalability and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar nonvolatile nitride cell structure is used, then the manufacturing process is simple, but the scalability is poor and sheet resistance is high
Solution Approach 1:
The patent transitions from a planar (2D) structure to a three-dimensional structure by recessing the channel region into the substrate. This vertical dimensionality change enables better scalability and reduced sheet resistance while maintaining manufacturing feasibility through standard semiconductor processing techniques adapted for vertical profiles.
Solution Approach 2:
The channel region is nested within the substrate by forming a recess, creating a hierarchical structure where the active channel is embedded in the bulk material. This nesting approach improves scalability by allowing tighter pitch while maintaining electrical performance.
2Device complexity
If a planar nonvolatile nitride cell structure is used, then the device structure is simple, but power consumption for program and erase operations is high
Solution Approach 1:
By moving to a vertical recessed channel structure, the electric field distribution is optimized to reduce power consumption during program and erase operations. The vertical configuration allows for more efficient charge trapping and release mechanisms compared to the planar structure.
3Ease of manufacture
If a planar nonvolatile nitride cell structure is used, then the fabrication process is straightforward, but sheet resistance is high
Solution Approach 1:
The recessed channel structure reduces sheet resistance by creating a vertical current path that bypasses the high-resistance surface layer. The channel is positioned deeper in the substrate where doping can be more effective, reducing resistance while maintaining fabrication compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances scalability and reduces power requirements for programming and erasing operations, addressing the limitations of conventional planar structures.
Implementation Method 1
These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride.
Implementation Method 2
The dielectric structures electrically isolate parts of the circuit from each other, in the absence of an electrical field to overcome the dielectric structures.
Data Source
AI summary
Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.