Recessed Channel Semiconductor Memory Cell Array
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in reducing the line widths of word and selection lines due to photolithography constraints and issues like punch through and leakage current, which affect the channel length and insulation layer formation.
Innovation Solution
A cell array structure is developed with a semiconductor substrate having active regions with different top surface levels, where word lines cross over one region and selection lines are formed on both sides of another region, with at least a portion over a transition region, allowing for longer channel lengths and reduced aspect ratio defects in the insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width of selection lines is reduced to increase integration density, then the integration density is improved, but punch through and leakage current occur due to short channel effect
Solution Approach 1:
The patent introduces a third dimension by forming a recessed channel structure in the semiconductor substrate. The channel is formed at a lower level than the surrounding substrate surface, creating a stepped structure. This dimensional change allows the channel length to be extended vertically while maintaining a compact planar footprint, thereby reducing leakage current without sacrificing integration density.
Solution Approach 2:
The patent changes the physical parameters of the channel structure by creating a recessed region with different depth and width characteristics. The channel width is reduced at the recessed portion while maintaining or increasing the effective channel length through the vertical dimension. This parameter transformation allows the channel to operate with longer effective length (reducing short channel effects) while occupying less planar area.
2Quantity of substance
If the line width of word lines is reduced to increase integration density, then the integration density is improved, but the manufacturing precision is limited by photolithography process
Solution Approach 1:
The patent moves the channel formation to a recessed region below the substrate surface. This allows the channel dimensions to be defined by etching depth and recess geometry rather than relying solely on photolithography line width control. The recessed channel structure enables precise dimensional control through selective etching processes, bypassing the resolution limits of photolithography for defining critical channel dimensions.
3Ease of manufacture
If a symmetric recessed channel structure is used, then the manufacturing process is simplified, but the aspect ratio of the recess region becomes large causing non-uniform insulation layer formation
Solution Approach 1:
The patent employs an asymmetric recessed channel structure where the channel is positioned offset from the center of the gate electrode. The recess region has different dimensions on opposite sides, creating an asymmetric profile. This asymmetry reduces the maximum aspect ratio of the recess structure, improving fill factors during insulation layer deposition and ensuring more uniform layer formation while maintaining the simplified manufacturing approach.
Data Source
AI summary
A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.