Recessed Channel Strained Semiconductor Device
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Solution Overview
Problem
Existing approaches to inducing strain in transistor channel regions are limited, as the stress-inducing layers are confined to heavily-doped source/drain regions, failing to contribute significantly to the channel region stress, particularly in the source/drain extension and gate electrode overlap areas.
Innovation Solution
A semiconductor device with a recessed channel region is developed, where stress-inducing material extends into the source/drain extension regions, creating a greater stress in the channel area, and the channel region is recessed with raised source/drain extension regions above the gate dielectric layer, allowing for improved stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If stress-inducing layers are confined to heavily-doped source/drain regions, then manufacturing is simplified, but stress contribution to the channel region is insufficient
Solution Approach 1:
The stress-inducing material is extended from the traditional planar source/drain regions into the vertical dimension by filling recesses that extend under the gate electrode. This three-dimensional configuration allows the stress-inducing material to occupy the source/drain extension regions and contribute stress to the channel region more effectively, resolving the contradiction between manufacturing simplicity and stress effectiveness.
Solution Approach 2:
Recesses are formed in the substrate before forming the stress-inducing material and gate electrode. This preliminary action creates predefined regions where the stress-inducing material will be deposited, ensuring it extends into the source/drain extension regions and provides adequate stress to the channel region while maintaining a structured manufacturing process.
2Reliability
If carrier mobility is enhanced through strain, then transistor performance increases, but device complexity increases
Solution Approach 1:
The stress-inducing material is selectively placed in specific regions (source/drain extension regions defined by recesses) rather than uniformly throughout the device. This localized approach enhances carrier mobility in the channel region where it is most needed while avoiding unnecessary complexity in other areas, achieving performance improvement with controlled device complexity.
3Stress or pressure
If stress-inducing material extends into source/drain extension regions, then channel stress is improved, but manufacturing precision requirements increase
Solution Approach 1:
The recesses are formed in the substrate before depositing the stress-inducing material, creating pre-defined boundaries and depths that guide the material placement. This preliminary structuring ensures the stress-inducing material extends into the source/drain extension regions with adequate precision while maintaining a manageable manufacturing process through sequential fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances carrier mobility, increases drive current, and reduces short channel effects, achieving a 10% relative stress-induced drive current gain and 9% increase in drive current Ion with reduced pocket/halo implant and drain-induced barrier lowering.
Implementation Method 1
epitaxially growing a stress-inducing layer having a larger lattice structure than the silicon, such as a layer of SiGe, within recessed regions in the source/drain regions
Data Source
AI summary
A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.