Recessed Channel Transistor Height Control via Wet-Etching

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Solution Overview

Problem

Existing methods for manufacturing semiconductor devices with recessed channel transistors face challenges in precisely adjusting the shape and height of the channel region, leading to issues with bur portion removal and optimal operation characteristics, particularly in maintaining the threshold voltage and on-current.

Innovation Solution

A method involving the formation of a first and second recess in a semiconductor substrate, followed by the deposition of insulating films and wet-etching to adjust the height of the thin film portion acting as the channel region, ensuring precise control over the channel region's dimensions and removal of bur portions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing methods are used to form recessed channel transistors, then the manufacturing process can be completed, but the shape and height of the channel region cannot be precisely adjusted

Engineering Contradiction:
Improvechannel region shape and heightVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent divides the channel region formation into multiple steps: forming a first recess, depositing a first insulating film, forming a second recess, and performing selective wet-etching. This segmentation allows precise control over the channel region's shape and height by independently adjusting each process parameter.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by forming the first recess and first insulating film before creating the final channel structure. These preliminary structures serve as masks and etch stops that enable precise subsequent processing of the channel region.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If bur portion is completely removed from element isolation region, then transistor operation is improved, but channel region height control becomes difficult

Engineering Contradiction:
Improvetransistor operationVSAvoidchannel region height
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a first insulating film as an intermediary layer between the element isolation region and the channel region. This insulating film acts as an etch stop that allows complete removal of the bur portion while preventing over-etching that would compromise the channel region height, thus resolving the contradiction between bur portion removal and height control.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If gate length is reduced for miniaturization, then device density increases, but short channel effect causes threshold voltage reduction and off-current increase

Engineering Contradiction:
Improvedevice densityVSAvoidthreshold voltage and off-current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from a planar channel structure to a recessed channel structure by etching the channel region below the gate electrode level. This dimensional change increases the effective channel length without increasing the planar footprint, thereby maintaining device density while improving threshold voltage control and reducing off-current through enhanced gate control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the precise adjustment of the channel region's height and shape, stabilizing current flow and operation characteristics, thereby enhancing the performance of recessed channel transistors by removing bur portions and maintaining optimal threshold voltage.

Implementation Method 1

An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion

Methodology Applied
Scientific EffectWet-etching:

Data Source

PatentUS8043903B2Method of manufacturing semiconductor device
Publication Date: 2011.10.25 MICRON TECHNOLOGY INC
  • US8043903B2 patent drawing
  • US8043903B2 patent drawing
  • US8043903B2 patent drawing

AI summary

A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion.