Recessed Semiconductor Chip Edge Structure for Wiring Layer Protection

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Solution Overview

Problem

Semiconductor chips face instability and reliability issues during the sawing process due to exposure of wiring layers, leading to potential failure.

Innovation Solution

The semiconductor chip design incorporates a recessed region in the edge area with a cover portion to protect the wiring layer, using insulating layers to cover the exposed side surfaces and prevent oxidation and peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the wiring layer is exposed in the edge region, then the sawing process can be performed, but the stability and reliability of the semiconductor chip deteriorates due to oxidation and peeling of the wiring layer

Engineering Contradiction:

Improvesawing processVSAvoidstability of wiring layer

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming the recessed region and positioning the cover structure to protect the wiring layer side surface before the sawing process occurs. This pre-positioning ensures that when the chip is cut, the wiring layer is already protected from exposure, preventing oxidation and peeling while allowing the sawing process to proceed effectively.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the wiring layer is covered completely, then the stability and reliability improves, but the sawing process becomes difficult to perform

Engineering Contradiction:

Improvestability of wiring layerVSAvoidsawing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by providing protective cover structures only at specific locations where the wiring layer side surface is exposed in the edge region, rather than covering the entire chip. This localized protection approach maintains wiring layer stability where needed while leaving other areas open for the sawing process to be performed effectively.

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If the side surface of the wiring layer is exposed, then the chip can be manufactured, but oxidation and peeling occur leading to failure

Engineering Contradiction:

Improvechip manufacturingVSAvoidoxidation and peeling of wiring layer

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of exposed wiring layer surfaces by introducing cover structures that transform the exposed, vulnerable surface into a protected interface. The cover structure material is selected to be compatible with the wiring layer, converting the harmful oxidation and peeling effects into a protected, stable configuration that prevents failure.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

4Reliability

If a cover structure is added to protect the wiring layer, then oxidation and peeling are prevented, but the device complexity increases

Engineering Contradiction:

Improveprotection from oxidation and peelingVSAvoidstructure of semiconductor chip

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies flexible shells and thin films by using thin film cover structures that conformally cover the wiring layer side surface in the recessed region. These thin film structures provide effective protection against oxidation and peeling while adding minimal structural complexity, as they can be deposited as thin conformal layers rather than bulky protective elements.

Inventive Principle:

Principle #30Flexible shells and thin films

Data Source

PatentUS12431442B2Semiconductor chips having recessed regions

Publication Date: 2025.09.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor chip includes a semiconductor substrate including a device region, and an edge region surrounding the device region, a device layer on the semiconductor substrate, a wiring layer on the device layer, a side surface of the wiring layer at least partially defining a recessed region that is in the edge region such that the side surface of the wiring layer is exposed by the recessed region, and an upper insulating layer on the wiring layer. The recessed region extends from a side surface of the device layer toward the device region. A first portion of the upper insulating layer covers the side surface of the wiring layer that is exposed by the recessed region.