Recessed Chip Insulation Structure for Creepage Distance Control
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Solution Overview
Problem
Current semiconductor devices with wide bandgap semiconductors face challenges in enhancing electrical characteristics and reliability due to issues with electric field concentration and discharge phenomena, particularly in thin chip configurations with limited creepage distances and inadequate insulation.
Innovation Solution
The semiconductor device incorporates a recessed portion on the chip surface and a sealing insulator with an anker portion, increasing creepage distance and improving insulation properties, while the chip's laminated structure with a semiconductor substrate and epitaxial layer helps in reducing electric field concentration and enhancing planar area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the chip thickness is reduced to achieve thinner device profiles, then the device compactness is improved, but the creepage distance is insufficient leading to inadequate insulation
Solution Approach 1:
The patent introduces a recessed portion that extends vertically into the chip substrate, creating a three-dimensional path for the sealing insulator. This vertical dimension allows the sealing insulator to achieve sufficient creepage distance by traveling down into the recessed portion and along its sidewalls, thereby maintaining insulation performance despite reduced overall chip thickness.
Solution Approach 2:
The sealing insulator is nested within the recessed portion of the chip substrate. The recessed portion acts as a cavity that houses the sealing insulator, allowing the insulator to be positioned within the chip structure rather than merely on the surface. This nesting arrangement maximizes the use of available space while achieving the required insulation characteristics.
2Reliability
If the creepage distance is increased to improve insulation, then the withstand voltage is enhanced, but the device area increases
Solution Approach 1:
Instead of increasing the planar surface area to achieve longer creepage distance, the patent utilizes the vertical dimension by forming a recessed portion that extends into the chip substrate. The sealing insulator follows this vertical path, achieving sufficient creepage distance through three-dimensional routing rather than lateral expansion, thereby maintaining compact device area.
Solution Approach 2:
The sealing insulator is implemented as a thin film structure that conformally coats the recessed portion and electrode. This thin film approach allows the insulator to achieve adequate thickness and creepage distance without requiring large planar dimensions, as the insulation path is optimized through the vertical recessed structure rather than horizontal spread.
3Reliability
If the electrode area is increased to reduce electric field concentration, then the electrical characteristics are improved, but the chip area占用 increases
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions: the recessed portion provides enhanced insulation locally, the sealing insulator offers localized electrical isolation, and the electrode maintains optimized geometry for electrical performance. This local differentiation allows each component to be optimized for its specific function without compromising overall chip area efficiency.
Data Source
AI summary
A semiconductor device includes a chip having a main surface, a recessed portion formed in the main surface, and a sealing insulator that covers the main surface, and that has an anker portion positioned in the recessed portion.