Recessed-Chip Semiconductor Package for Compact 3D Stacking
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving reduced horizontal and vertical sizes while maintaining reliability and durability, particularly in stacked semiconductor configurations.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip inserted into a recessed region of a second semiconductor chip, with subsequent chips stacked on the first chip, utilizing adhesive layers and a mold layer to stabilize the structure and reduce overall package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in conventional configurations, then integration density is improved, but package size (horizontal and vertical) increases
Solution Approach 1:
The patent applies nesting by inserting the first semiconductor chip into a recessed region formed in the second semiconductor chip. This allows one chip to be nested within another, achieving higher integration density while minimizing the increase in package volume. The recessed region enables the first chip to occupy space that would otherwise be empty or require additional packaging volume.
Solution Approach 2:
The patent transitions from conventional planar stacking to a multi-dimensional configuration by creating a recessed region that extends vertically into the second chip. This allows the first chip to be positioned at a different vertical level (z-dimension) rather than simply stacking chips flat on top of each other, thereby reducing the overall vertical height of the package while maintaining high integration.
2Quantity of substance
If recessed region depth is increased to accommodate first semiconductor chip, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a particular depth range for the recessed region (90 μm to 780 μm) that optimizes the balance between integration density and manufacturability. By defining this parameter within a specific range rather than requiring a single precise value, the design achieves high integration while accommodating normal variations in manufacturing processes.
3Reliability
If adhesive layers and mold layers are added to stabilize stacked structure, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functional layers (adhesive layers for bonding, mold layers for encapsulation and mechanical support) into an integrated structure that stabilizes the stacked chips. Rather than treating these as separate added components, they are merged into a unified package structure that provides both mechanical stability and environmental protection, thereby improving reliability without proportionally increasing complexity.
Data Source
AI summary
A semiconductor package includes first semiconductor chips stacked on a package substrate, a lowermost first semiconductor chip of the first semiconductor chips including a recessed region, and a second semiconductor chip inserted in the recessed region, the second semiconductor chip being connected to the package substrate.