Recessed Conductive Interconnect with Co-Planar Cap for IC Memory Integration
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Solution Overview
Problem
The integration of memory cells and logic devices on a single substrate poses challenges due to differences in conductive via height, leading to thicker insulating material requirements, which increases the aspect ratio of via openings, making them harder to fill and resulting in defective vias and reduced product yields and performance.
Innovation Solution
The formation of recessed conductive interconnect structures within insulating material with a conductive cap layer, where the cap layer's surface is co-planar with the insulating material's surface, allowing for proper electrical coupling to memory cells and reducing the need for thicker insulating layers in logic regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thicker insulating material is formed in logic regions to accommodate memory cell heights, then memory and logic devices can be co-integrated on a single substrate, but the aspect ratio of via openings increases making them harder to fill properly
Solution Approach 1:
The conductive interconnect structure is segmented into two parts: a lower portion embedded in the insulating material and an upper protruding portion. This segmentation allows the via opening to be filled only up to a certain level, avoiding the need to fill the entire height through the thick insulating layer, thereby reducing the effective aspect ratio and improving filling quality.
Solution Approach 2:
The conductive structure transitions from a purely vertical via configuration to a multi-level structure with both embedded and protruding portions. This dimensional change allows the interconnect to accommodate the thick insulating material while maintaining proper via filling by extending the conductive path laterally at the protruding level.
2Adaptability or versatility
If thicker insulating material is formed in logic regions, then memory cell height differences can be accommodated, but conductive via aspect ratio increases leading to more defective vias and reduced product yields
Solution Approach 1:
Dividing the conductive interconnect into embedded and protruding portions reduces the via aspect ratio, improving fill quality and reducing defective vias, which directly enhances product yield while maintaining height accommodation capability.
Solution Approach 2:
By changing the geometric parameters of the conductive structure (creating a protruding portion), the effective via depth is reduced, lowering the aspect ratio and improving manufacturing reliability without sacrificing the ability to accommodate height differences.
3Ease of manufacture
If standard conductive via formation is used in thicker insulating material, then process simplicity is maintained, but via filling becomes more difficult and defective
Solution Approach 1:
The via filling process is segmented into two stages: filling the embedded portion through the insulating material, and then adding the protruding portion on top. This segmentation makes the filling process more manageable and less prone to defects while maintaining relative process simplicity.
Solution Approach 2:
The conductive structure is prepared in advance with the protruding portion configuration before the filling process, which facilitates easier and more complete via filling by reducing the effective depth that needs to be filled through the thick insulating material.
Data Source
AI summary
One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.