Recessed Conductive Layer for Fine Pitch Semiconductor Bonding
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Solution Overview
Problem
Current semiconductor manufacturing processes face limitations in reducing bump pitch and increasing input/output (I/O) count for semiconductor dies, primarily due to the constraints imposed by solder resist layers during the reflow process.
Innovation Solution
A method involving the formation of a partially-etched conductive layer recessed within a substrate, allowing for closer spacing of interconnects and eliminating the need for solder registration openings, which enables finer pitch and higher I/O density by using a recessed substrate with prepreg walls to contain bump material during reflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder registration openings (SRO) are used to contain bump material during reflow, then bump material is contained effectively, but bump pitch cannot be reduced and I/O count is limited
Solution Approach 1:
The patent removes the solder registration opening (SRO) layer entirely, extracting the harmful constraint that limited bump pitch. Instead of using SRO to contain bump material, the invention uses the recessed substrate structure itself to provide containment, allowing bumps to be placed directly on the substrate surface without the intermediary SRO layer, thereby enabling finer pitch and higher I/O density
Solution Approach 2:
The patent transitions from a planar two-dimensional bump placement approach to a three-dimensional approach by creating recesses in the substrate. The bump material is contained within these recesses, utilizing the vertical dimension (depth) for containment rather than relying on lateral constraints from SRO openings. This dimensional change enables much tighter bump spacing while maintaining effective material containment during reflow
2Productivity
If bump pitch is reduced to increase I/O count, then device density increases, but bump material containment becomes difficult without SRO
Solution Approach 1:
By creating recesses in the substrate, the patent uses the vertical dimension to contain bump material. The recess depth provides a physical barrier that prevents bump material from spreading laterally during reflow, enabling tight bump pitch without requiring lateral containment structures like SRO. This three-dimensional containment approach allows bumps to be placed much closer together while maintaining manufacturing precision
Solution Approach 2:
The patent applies local quality by creating recesses specifically at the bump locations rather than uniformly across the entire substrate. Each recess is localized to contain its corresponding bump material, providing precise containment exactly where needed. This localized approach enables high-density bump arrangements while maintaining effective material containment through the substrate geometry itself
3Productivity
If recessed substrate structure is used to contain bump material, then SRO is eliminated and bump pitch can be reduced, but substrate fabrication complexity increases
Solution Approach 1:
The patent changes the physical parameters of the substrate by introducing controlled recesses with specific depths and dimensions. By optimizing the recess depth (sufficient to contain bump material) and width (matching bump pitch requirements), the substrate provides effective bump containment while maintaining compatibility with standard semiconductor fabrication processes. This parameter optimization balances the added fabrication complexity with the significant gains in I/O density and bump pitch reduction
Data Source
AI summary
A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.