Redistribution Layer with Recessed Connectors for Semiconductor Dies
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Solution Overview
Problem
The conventional method of forming a redistribution layer on semiconductor dies is costly due to the high number of photolithography steps and can result in undesirable metal profiles from wet etching, leading to space inefficiencies and increased manufacturing costs.
Innovation Solution
A method involving etching a trench around a through wafer interconnect via stud on the semiconductor die's backside, filling it with conductive metal to form bond pads and traces, and reducing the number of photolithography steps by using a trench etching and dielectric layer management process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography steps are used to form redistribution layer, then bond pads and conductive traces can be formed, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the expensive photolithography steps from the conventional redistribution layer formation process. Instead of using multiple photolithography steps to pattern bond pads and conductive traces, the invention uses a single etch step to directly form these features, thereby removing the harmful cost factor while preserving the essential functionality of forming precise conductive structures.
Solution Approach 2:
The patent replaces expensive, complex photolithography processes with simpler, cheaper etching processes. The etch masks used in the new method are temporary and disposable, applied only during the etching step and then removed, whereas photolithography involves expensive photoresist materials and multiple processing steps. This substitution dramatically reduces manufacturing cost while achieving the same functional result.
2Ease of manufacture
If wet etching is used to etch metal layer, then bond pads and traces can be formed, but undercutting occurs leading to undesirable metal profile
Solution Approach 1:
The patent changes the etching parameters by switching from wet etching to dry etching. This parameter change fundamentally alters the etching mechanism from a chemical solution-based process that causes undercutting to a vapor-phase process that provides anisotropic, directional etching. The dry etching process allows for precise control of etch depth and profile, eliminating the undercutting problem while maintaining ease of manufacture.
3Area of stationary object
If through wafer interconnect via studs are used, then space occupied by electrical circuits is reduced, but additional processing steps are required
Solution Approach 1:
The patent merges the formation of bond pads and conductive traces with the via stud structure itself. Instead of treating these as separate features requiring separate processing steps, the invention uses a single etch step that simultaneously defines both the via stud openings and the bond pad/conductive trace patterns. This merging eliminates redundant processing steps while achieving compact electrical circuit layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and eliminates undercutting issues, allowing for more compact and efficient redistribution layers on semiconductor dies, enhancing space utilization and reducing the footprint of electronic devices.
Implementation Method 1
A first etch mask is formed over the backside of the substrate and around the via stud
Implementation Method 2
a trench is etched into the backside of the substrate to produce a trench arranged around a through wafer interconnect via stud
Implementation Method 3
filling it with conductive metal to form bond pads and traces
Data Source
AI summary
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.