Recessed Decoupling Capacitors in Shallow Trench Isolation
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Solution Overview
Problem
Current semiconductor fabrication processes are unable to form planar decoupling capacitors with adequate decoupling capacitance to effectively protect integrated circuits from current and voltage noise without consuming excessive circuit area.
Innovation Solution
The method involves fabricating decoupling capacitors in shallow trench isolation trenches, where the bottom plate is formed from the substrate and the top plate is recessed below the channel region, with a dielectric layer thicker on the sidewalls and thinner on the bottom to minimize sidewall capacitance and isolate the capacitor from adjacent active device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar decoupling capacitors are formed with larger area to achieve adequate decoupling capacitance, then noise protection capability is improved, but circuit area consumption increases
Solution Approach 1:
The patent transitions from planar capacitors to three-dimensional recessed capacitor structures by etching trenches into the substrate and forming capacitor plates at different depths. This vertical dimensionality change allows achieving higher capacitance values without proportionally increasing the horizontal footprint, directly resolving the contradiction between noise protection capability and circuit area consumption.
Solution Approach 2:
The capacitor structure is nested within the substrate by forming recessed trenches and embedding capacitor plates within the substrate volume. This nesting approach utilizes the substrate's vertical space, allowing the capacitor to be integrated within the existing circuit architecture without requiring additional surface area, thereby maintaining compact circuit design while providing adequate decoupling capacitance.
2Reliability
If decoupling capacitors are formed with higher capacitance density, then noise protection per unit area is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the decoupling capacitor formation process with the existing shallow trench isolation (STI) process. By integrating capacitor trench formation into the STI workflow and using the same dielectric materials and processing steps, the manufacturing complexity is minimized while achieving high capacitance density. This merging of processes eliminates the need for separate capacitor fabrication sequences.
Solution Approach 2:
The substrate regions serve multiple functions: they provide both shallow trench isolation for device separation and host decoupling capacitor structures. The dielectric layers serve dual purposes as both isolation material and capacitor dielectric. This multi-functionality reduces overall device complexity by eliminating redundant structures and processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of high-capacity decoupling capacitors that effectively reduce noise impact while minimizing vertical series resistance and electrical cross-talk, enabling efficient noise protection without significant area consumption.
Implementation Method 1
decoupling capacitors are formed on the chip to shunt the noise through the capacitor, thereby reducing the effect of the noise on the protected area
Implementation Method 2
a dielectric layer thicker on the sidewalls and thinner on the bottom to minimize sidewall capacitance and isolate the capacitor from adjacent active device operation
Data Source
AI summary
A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.