Recessed Deep Vias for Low-Resistance Backside Power Delivery
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Solution Overview
Problem
Deep vias in integrated circuits (ICs) exhibit high resistance and unwanted capacitance, which negatively impact the performance of transistor circuits due to their full-length extension and proximity to channel regions.
Innovation Solution
The deep vias are recessed to include an interface region and non-interface regions, with the non-interface regions extending a shorter distance than the full length, reducing resistance and capacitance by minimizing the interface with circuit interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep vias extend the full length from the second die surface to the first die surface, then power distribution is achieved, but resistance and capacitance increase
Solution Approach 1:
The via structure is segmented into two distinct regions: a first region extending from the second die surface to a intermediate depth, and a second region extending from the first die surface to meet the first region. This segmentation allows the via to be recessed from the first die surface, reducing the exposed interface area that causes capacitance while maintaining the through-die power connection.
Solution Approach 2:
The via structure implements local quality by having different regions serve different functions: the first region (deeper portion) provides the primary power connection with minimal capacitance exposure, while the second region (shallower portion) provides the interface connection to circuit interconnects. This localized differentiation optimizes both power distribution and electrical characteristics.
Data Source
AI summary
Deep vias may be employed on a die to connect transistor circuits on a front side to a power distribution network on a back side. Deep vias extending from a second die surface to a first die surface over an entire length may have high resistance interfaces to circuit interconnects that couple the deep vias to transistor circuits. Deep vias adjacent to transistor channel regions in the transistor circuits may also cause unwanted capacitance. An exemplary deep via includes an interface region and at least one non-interface region, where the interface region includes an interface between the deep via and a circuit interconnect, and the at least one non-interface region extends a second distance that is less than the distance between the first die surface and the second die surface. In this manner, capacitance is reduced, and resistance may be reduced.