Recessed Die Pads for Low-Height Stack Interconnections
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in reducing package height while maintaining electrical connectivity, as they require stringent alignment, surface cleaning, and planarization, which are difficult and costly to achieve, especially in vertically stacked die configurations.
Innovation Solution
The use of recessed pads on semiconductor dies with insulating materials for direct dielectric bonding and a conductive structure formed through a monolithic via and protrusions, which allows for reduced vertical separation and eliminates the need for additional interposing structures like solder bumps, enabling smaller package heights and reliable die-to-die interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solder interconnects are used for electrically coupling dies in a vertical stack, then electrical connectivity between dies is achieved, but the overall package height significantly increases
Solution Approach 1:
The patent extracts and eliminates the solder interconnect layer from the vertical stack structure. Instead of using separate solder bumps to connect dies, the invention integrates the conductive function directly into the die stacking interface through recessed pad structures, removing the need for intermediate solder layers and thereby reducing package height
Solution Approach 2:
The patent implements nesting by placing recessed conductive pads within recesses formed in the die surfaces. The upper die is positioned such that its bottom surface nests into the recess of the lower die, with the conductive pad making direct contact. This nested configuration eliminates the need for protruding interconnect structures, reducing overall package height while maintaining electrical connectivity
2Length of moving object
If hybrid bonding techniques are used to reduce package height, then vertical separation between dies is reduced, but stringent requirements for alignment, surface cleaning, and planarization are imposed
Solution Approach 1:
The patent applies preliminary action by pre-forming recesses and placing conductive pads within them on each die before stacking. This advance preparation creates self-aligning features that guide the stacking process, eliminating the need for high-precision alignment during assembly. The recesses act as mechanical guides that automatically position the upper die correctly over the lower die
Solution Approach 2:
The patent replaces the complex, expensive hybrid bonding process with a simpler, more robust mechanical stacking approach using recessed pads. The solution accepts slightly reduced process sophistication in exchange for dramatically simplified manufacturing requirements, making the process more accessible and cost-effective while achieving the same height reduction goal
3Reliability
If additional interposing structures like solder bumps are used for die interconnections, then electrical connectivity is ensured, but the package footprint and height increase
Solution Approach 1:
The patent merges the electrical connection function with the mechanical support function into a single integrated structure. The recessed conductive pad serves both as the structural element that mechanically supports the upper die and as the electrical interconnect. This consolidation eliminates the need for separate solder bumps or wire bonds, reducing package volume while ensuring reliable electrical connectivity
Data Source
AI summary
Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.