Recessed Digit Line Memory Array Integration
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Solution Overview
Problem
Conventional finFET memory array architectures face challenges in achieving high integration due to the limited space for charge-storage devices and digit lines, leading to inefficiencies in current flow and storage capacity.
Innovation Solution
The proposed solution involves creating memory arrays with recessed digit lines and charge-storage devices, where the digit lines are positioned entirely below the charge-storage devices, allowing for higher integration by enabling the charge-storage devices to extend over the digit lines, and using finFET transistors with a unique pedestal structure and doping levels to optimize current flow and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional finFET memory array architectures are used, then the structure is simpler and easier to manufacture, but the integration density is limited and space for charge-storage devices and digit lines is insufficient
Solution Approach 1:
The patent implements recessed digit lines that extend vertically below the charge-storage devices, transitioning from a planar two-dimensional layout to a three-dimensional vertical architecture. This dimensional change allows digit lines to pass underneath capacitors, effectively doubling the usable space and enabling higher integration density without increasing the lateral footprint of the memory cell.
Solution Approach 2:
The recessed digit lines are nested within the vertical structure of the memory cell, positioned below the charge-storage devices. This nesting arrangement allows the digit lines to occupy the same lateral space as the capacitors but at a different vertical level, effectively hiding the interconnect structure within the existing cell architecture and maximizing space utilization.
2Reliability
If charge-storage devices and digit lines are positioned in conventional configurations, then manufacturing is easier, but resistance in digit lines is higher and current flow efficiency is reduced
Solution Approach 1:
By positioning digit lines in a recessed vertical configuration below the charge-storage devices, the patent creates shorter and more direct current paths. This dimensional reconfiguration reduces the lateral distance electrons must travel, lowering resistance and improving current flow efficiency without requiring fundamentally different manufacturing processes.
Solution Approach 2:
The patent modifies the vertical positioning parameter of the digit lines, moving them from a lateral configuration to a recessed vertical configuration. This parameter change optimizes the electrical characteristics by reducing path length and resistance, while the fabrication process remains compatible with existing semiconductor manufacturing techniques through sequential processing steps.
Data Source
AI summary
Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.