Recessed Transistor Drain and Source for Silicide Control
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Solution Overview
Problem
The continuous reduction in transistor dimensions poses challenges in maintaining low sheet and contact resistivity in drain and source regions while ensuring channel controllability, with existing stress transfer mechanisms being limited by deposition capabilities and resulting in reduced performance gain, especially for transistors with gate lengths of 50 nm and less.
Innovation Solution
A recessed transistor configuration is implemented, where the drain and source regions are formed with a reduced height to position highly stressed dielectric material closer to the channel region, enhancing strain-induced performance and reducing fringing capacitance, while maintaining control over silicidation to avoid complete silicidation of the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is reduced to increase operating speed and packing density, then the operating speed and packing density are improved, but the sheet and contact resistivity in drain and source regions increases and channel controllability deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming recesses in the drain and source regions, creating a stepped structure where the active channel region remains at a higher elevation than the silicided contact regions. This dimensional change allows the channel length to be reduced for higher speed while the vertical separation maintains channel controllability and reduces parasitic capacitance between the gate and contact regions.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical levels: the channel region at a higher level and the drain/source contact regions recessed to a lower level. This segmentation allows independent optimization of the channel for controllability and the contact regions for low resistance, resolving the contradiction between speed and reliability.
2Power
If the gate dielectric thickness is reduced to increase capacitive coupling, then the drive current capability is improved, but leakage currents increase exponentially
Solution Approach 1:
Instead of further reducing the gate dielectric thickness, the patent uses the vertical dimension by recessing the drain and source regions. This creates additional capacitive coupling area through the vertical walls of the recesses while maintaining the same dielectric thickness, thereby improving drive current without increasing leakage currents.
3Reliability
If highly stressed dielectric material is deposited to enhance strain in the channel region, then charge carrier mobility is improved, but deposition capabilities are limited and performance gain is reduced
Solution Approach 1:
The patent utilizes the vertical walls of the recessed drain and source regions to deposit highly stressed dielectric material. This vertical surface area provides an extended interface for stress transfer to the channel region, enhancing charge carrier mobility while working within conventional deposition capabilities by using the available vertical space efficiently.
Solution Approach 2:
The patent applies highly stressed dielectric material specifically to the vertical walls of the recessed regions adjacent to the channel, concentrating the strain effect where it is most needed. This localized application of stress maximizes the mobility enhancement in the channel region without requiring excessive deposition throughout the entire structure.
4Reliability
If metal silicide is formed in drain and source regions to reduce sheet and contact resistivity, then the contact resistivity is improved, but complete silicidation of the gate electrode must be avoided to maintain threshold voltage control
Solution Approach 1:
The patent uses the vertical recess structure to spatially separate the silicided contact regions from the gate electrode. The recesses allow metal silicide to be formed in the drain and source regions at a lower elevation without the silicide encroaching onto or completely siliciding the gate electrode, thereby maintaining threshold voltage control while achieving low contact resistivity.
Solution Approach 2:
The recessed structure acts as an intermediary spatial buffer between the silicided contact regions and the gate electrode. This intermediate vertical space allows the silicidation process to proceed to completion in the contact regions without the harmful side effect of complete gate silicidation, enabling independent optimization of both regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility and drive current capability by increasing the strain in the channel region and reducing series resistance, while minimizing threshold variability and fringing capacitance, thus improving transistor performance without increasing process complexity.
Implementation Method 1
creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed
Implementation Method 2
reducing fringing capacitance, thus improving transistor performance
Implementation Method 3
metal silicide formation in transistors... providing low sheet and contact resistivity in drain and source regions
Data Source
AI summary
During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.