Recessed DRAM Conductor Structure for Lower GIDL and Resistance
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Solution Overview
Problem
Recessed access devices in DRAMs face issues with gate-induced drain leakage (GIDL) due to a flat top surface of conductors and high resistance features when the capping layer is larger, while a larger conductor proportion leads to higher resistance issues.
Innovation Solution
A semiconductor structure with a concave substrate featuring a conductor having a stepped surface, where the first top surface is closer to the dielectric layer, and a capping layer with specific surface and bottom surface configurations, reducing GIDL and achieving low resistance through a manufacturing method involving a sacrificial layer and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the proportion of the conductor is larger, then the resistance is lower, but gate-induced drain leakage (GIDL) problems occur
Solution Approach 1:
The patent applies curvature by forming a stepped surface on the conductor instead of a flat top surface. The stepped surface includes a first portion closer to the gate electrode and a second portion farther away, creating a non-linear geometric profile that reduces the electric field concentration at the conductor-gate interface, thereby suppressing GIDL while maintaining low resistance through adequate conductor proportion
2Object-affected harmful factors
If the proportion of the capping layer is larger, then gate-induced drain leakage is reduced, but the resistance increases
Solution Approach 1:
The patent applies local quality by creating different portions of the conductor with different characteristics. The first portion (closer to gate) has specific dimensions to control electric field and reduce GIDL, while the second portion (farther from gate) provides adequate conductive cross-section for low resistance. This localized differentiation allows simultaneous optimization of both GIDL suppression and resistance reduction
Data Source
AI summary
A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.