Recessed Field Plate Layout for Lower GaN Gate-Drain Capacitance
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Solution Overview
Problem
Existing GaN transistors face performance variations due to misalignment of gate channels and field plates, leading to inconsistencies in capacitances, gain, cut-off frequency, and trapping effects, which affect device reliability and efficiency in RF and power applications.
Innovation Solution
The implementation of self-aligned source-connected field plates with a recessed portion relative to gate-connected field plates, utilizing a surface passivation layer with multiple dielectric sub-layers for precise etching, ensures accurate alignment and reduces gate-drain capacitance, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional field plate alignment methods are used, then manufacturing process is simpler, but manufacturing precision deteriorates due to misalignment of gate channel and field plate
Solution Approach 1:
The patent applies preliminary action by forming the field plate structure before the gate electrode, using the field plate as a self-aligned mask and reference for subsequent gate patterning. This ensures precise alignment without requiring separate alignment steps, resolving the contradiction between alignment precision and process complexity
Solution Approach 2:
The field plate structure serves multiple functions: it defines the alignment reference, acts as a mask for gate patterning, and provides the final aligned structure. This self-service approach eliminates the need for separate alignment processes, achieving high precision while maintaining fabrication simplicity
2Reliability
If field plate extends fully over gate electrode, then electric field distribution is altered, but gate-drain capacitance increases
Solution Approach 1:
The patent applies local quality by creating a recessed portion in the field plate directly over the gate electrode, while maintaining field plate extension at the drain-side gate edge. This localized modification reduces gate-drain capacitance in the critical region while preserving the electric field distribution benefits where needed, resolving the contradiction between reliability and energy loss
3Manufacturing precision
If multiple alignment steps are used, then alignment precision improves, but manufacturing time increases
Solution Approach 1:
The patent merges multiple alignment functions into a single self-aligned process where the field plate structure simultaneously serves as the alignment reference, the mask for gate patterning, and the final aligned structure. This consolidation eliminates sequential alignment steps, improving both precision and productivity by removing the trade-off between them
Data Source
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Figure 3A~3B
AI summary
A semiconductor device includes a semiconductor substrate (110) with an upper surface and a channel, source (141) and drain (146) electrodes over the upper surface of the semiconductor substrate, a passivation layer (130) between the source and drain electrodes, a gate electrode (160) between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.