Recessed Field Plate GaN Transistors for Stable Short-Gate Fabrication
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Solution Overview
Problem
Fabricating high-power field effect transistors (FETs) with short gate lengths using gallium nitride (GaN) on silicon carbide (SiC) substrates is challenging due to transparency issues and non-uniformity, and dielectric layers experience plasma damage and etch-induced thickness variations during fabrication, affecting performance and reliability.
Innovation Solution
A transistor device structure and fabrication method involving multiple dielectric layers, where damaged dielectric layers are removed or covered to prevent plasma damage, with a fourth dielectric layer separating the field plate from the semiconductor substrate, ensuring precise thickness control and reducing charge carrier trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dry etch processes are used to fabricate dielectric layers, then device functionality is achieved, but plasma damage and etch-induced thickness variation occur
Solution Approach 1:
The patent segments the dielectric layer fabrication into multiple separate dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with different functions. Each layer is formed and processed independently, allowing selective removal of damaged portions from specific layers without affecting others, thereby maintaining thickness uniformity while achieving device functionality.
Solution Approach 2:
The patent extracts and removes damaged portions of dielectric layers (first portions of first and third dielectric layers, second portion of third dielectric layer) that have been affected by plasma damage during dry etching. This selective extraction eliminates the harmful effects of plasma damage while preserving the functional integrity of the device.
2Ease of manufacture
If photolithography alone is used to fabricate short gate lengths, then fabrication simplicity is maintained, but manufacturing precision deteriorates for GaN-on-SiC substrates
Solution Approach 1:
The patent introduces multiple dielectric layers as intermediary structures between the substrate and the gate structure. These dielectric layers (particularly the third dielectric layer formed directly on the substrate) serve as etch stop layers and protective barriers during subsequent processing, enabling precise gate length definition while protecting the substrate from damage.
3Device complexity
If dielectric layers are exposed to plasma during dry etching, then device structure is formed, but plasma damage occurs affecting performance
Solution Approach 1:
The patent applies beforehand cushioning by forming protective dielectric layers (second dielectric layer, third dielectric layer) before subsequent dry etching processes. These layers act as protective barriers that prevent plasma damage from reaching underlying layers and the substrate, while still allowing the necessary device structure to be formed through controlled etching of the protective layers themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves dielectric layer thickness uniformity, reduces charge carrier trapping, and enhances threshold voltage stability, addressing the challenges of fabricating reliable high-power FETs with short gate lengths on GaN/SiC substrates.
Implementation Method 1
performing a first wet etch to form a third opening and a fourth opening in the first dielectric layer
Data Source
AI summary
A transistor device and method of fabrication are provided, where the transistor device may include a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a third dielectric layer disposed on the second dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate in the gate channel, and a field plate disposed overlapping the gate structure. The gate may be defined via an opening that extends through the first, second, and third dielectric layers. Portions of the first and second dielectric layers may be interposed directly between the gate structure and the surface of the semiconductor substrate. A portion of the field plate may be disposed in a field plate channel at least partially defined via a second opening that extends through the second dielectric layer and the third dielectric layer.