Recessed FinFET Metal Gate Height Control with Sacrificial Gate Decoupling
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Solution Overview
Problem
In the semiconductor industry, particularly in FinFET manufacturing, controlling the height of the recessed metal gate structure is challenging due to its dependence on the sacrificial gate electrode profile, which affects device performance and requires precise adjustment to achieve desired threshold voltages for both n-channel and p-channel FETs.
Innovation Solution
A method is developed to control the height of the recessed metal gate structure by adjusting the profile of the sacrificial gate electrode, involving a series of sequential processes including ion implantation, mask layer formation, fin structure patterning, sacrificial gate formation, and subsequent etching and deposition steps to achieve precise metal gate recessing and work function adjustment layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal gate structure is formed by gate replacement technology, then the device performance is improved, but the control of recessed metal gate height becomes challenging due to dependence on sacrificial gate electrode profile
Solution Approach 1:
The patent introduces an intermediary etch stop layer (silicon nitride layer) between the sacrificial gate electrode and the metal gate structure. This intermediary layer acts as a mediator that decouples the metal gate height control from the sacrificial gate profile, allowing independent control of the recessed metal gate height through etching depth control rather than relying on sacrificial gate dimensions.
Solution Approach 2:
The gate structure is segmented into multiple functional layers: the sacrificial gate electrode, the etch stop layer, and the metal gate structure. This segmentation allows each layer to serve its specific function independently, with the etch stop layer specifically responsible for controlling the recessed metal gate height, while the sacrificial gate focuses on defining the gate pattern.
2Manufacturing precision
If the sacrificial gate electrode profile is adjusted to control metal gate height, then the recessed metal gate height control is improved, but the device complexity increases due to additional process steps
Solution Approach 1:
The etch stop layer is designed to be selectively removed by a specific etching process that automatically stops when it encounters the underlying layer, providing self-regulating height control. The layer serves its own purpose of defining the etch depth without requiring additional measurement or control steps.
Solution Approach 2:
The patent changes the material parameter of the gate structure by introducing silicon nitride as the etch stop layer material, which has distinct etching characteristics compared to surrounding materials. This parameter change enables selective etching and automatic process stopping, simplifying the overall control mechanism.
3Adaptability or versatility
If different metal structures are used for n-channel and p-channel FETs, then the threshold voltage adjustment is improved, but the manufacturing consistency becomes challenging
Solution Approach 1:
The patent applies local quality by allowing different metal gate structures and materials to be used in different regions (n-channel vs. p-channel FETs) while maintaining consistent recessed height control through the universal etch stop layer mechanism. Each region can be optimized for its specific electrical characteristics while sharing the same height control approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise control of the metal gate structure, enabling the fabrication of FinFETs with desired threshold voltages, improving device performance and manufacturing efficiency by ensuring consistent metal gate profiles regardless of the underlying metal structures.
Implementation Method 1
ion implantation
Implementation Method 2
conductive layers are formed on the gate dielectric layer to fully fill the gate space
Data Source
AI summary
In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.