Recessed Channel FinFET Layout for Dense Memory Periphery
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Solution Overview
Problem
Current memory devices face challenges in scaling and reducing size due to limitations in the design and fabrication of fin field-effect transistor (FinFET) devices, particularly in the periphery area of memory arrays, where conventional transistors occupy larger layout areas.
Innovation Solution
The integration of recessed channel FinFET devices with a recessed metal gate and channel structure, allowing for smaller layout areas and enhanced feature density through techniques like pitch double and pitch quad processes, combined with the use of materials like TiN for the metal gate and polysilicon for work function control, enables efficient scaling and integration with memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional transistor designs are used in periphery areas, then manufacturing processes are simpler, but device size and layout area are larger
Solution Approach 1:
The patent implements a nested structure where the gate is recessed into the substrate and fins are formed within the gate recess, creating a multi-level nested arrangement. This nesting allows the transistor components to occupy overlapping vertical spaces, reducing the horizontal layout area while maintaining all necessary functional elements
Solution Approach 2:
The patent transitions from a planar two-dimensional transistor layout to a three-dimensional structure by recessing the gate into the substrate and forming vertical fins. This dimensional change allows the channel to extend vertically along the fin structures, increasing the effective channel area without proportionally increasing the horizontal footprint
2Quantity of substance
If feature density is increased in periphery areas, then space utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by first forming the gate recess and filling it with conductive material before forming the fins. The gate structure is established in advance as a template that guides subsequent fin formation, ensuring precise alignment and spacing. This sequential approach with preliminary structuring reduces the precision requirements for simultaneous multi-feature patterning
Solution Approach 2:
The patent segments the transistor formation into distinct sequential steps: gate recess formation, gate electrode deposition, fin formation, and source/drain region creation. Each segment is processed independently with optimized parameters, allowing high feature density to be achieved through cumulative precision rather than requiring all features to be patterned simultaneously at ultra-fine dimensions
Data Source
AI summary
A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.