Recessed Gate Semiconductor Structure for Higher Channel Current
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Solution Overview
Problem
As semiconductor devices shrink, the reduced gate size leads to decreased current through the channel, limiting performance and necessitating larger chip areas to maintain or improve performance.
Innovation Solution
The introduction of recesses in the substrate allows for an increased effective channel width without expanding the gate active region, achieved by forming a gate structure that covers these recesses and substrate surfaces, thereby enhancing sidewall channels and current Ion-Ioff.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of gate structure is reduced, then the device size becomes smaller, but the current through the channel decreases and device performance deteriorates
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional structure by forming recesses in the substrate and covering them with gate structures. This vertical dimensionality change allows the channel to extend into the recesses, increasing the effective channel width without increasing the lateral footprint of the device, thus maintaining performance while reducing device size.
Solution Approach 2:
The channel is segmented into multiple portions by forming several recesses in the substrate, each covered by a gate structure. This segmentation creates multiple parallel current paths through the channels in the recesses, increasing the total effective channel width and current capacity without increasing the overall device lateral dimensions.
2Volume of moving object
If the size of gate structure is reduced, then the device size becomes smaller, but the chip area occupied increases to maintain performance
Solution Approach 1:
By utilizing the vertical dimension through substrate recesses, the patent increases the effective channel width in the vertical direction rather than expanding horizontally. This allows the device to maintain or improve performance without increasing the lateral chip area, as the additional channel capacity is achieved through depth rather than width.
Solution Approach 2:
The gate structures are nested within the recesses formed in the substrate, with the gate dielectric layer and gate conductive layer conformally coating the recess walls and bottom. This nesting arrangement maximizes the use of vertical space within the existing lateral boundaries, increasing channel capacity without requiring additional chip area.
3Length of moving object
If multiple recesses are formed in the substrate with gate structures, then the effective channel width increases, but the device complexity increases
Solution Approach 1:
The gate structure is designed as a universal, multi-functional component that can be replicated across multiple recesses. The same gate dielectric layer and gate conductive layer configurations are used for each recess, allowing standardized fabrication processes to be applied repeatedly. This modularity increases effective channel width through replication rather than through uniquely complex structures.
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.