Recessed Active Gate Contacts for Self-Aligned Transistor Scaling
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the constraint on lithographic processes when scaling down multi-gate transistors, particularly in achieving precise feature patterning and spacing, which limits the ability to place gate contacts over active regions without increasing gate dimensions or compromising registration accuracy.
Innovation Solution
The approach involves forming gate contact structures directly over active portions of gate electrodes by recessing contact metals in trench contacts and introducing a dielectric material with different etch characteristics, allowing for self-aligned contact formation without the need for additional lithographic steps or separate gate contact layers, thus enabling direct contact from a metal interconnect layer without shorting to adjacent source-drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate contact structures are formed over inactive portions of gates using conventional lithographic processes, then registration accuracy can be maintained, but additional layout area is required and manufacturing complexity increases
Solution Approach 1:
The gate contact structure is formed to contact the gate electrode directly, where the gate structure itself serves as the contact target without requiring separate contact regions. The recessed gate structure with exposed gate electrode enables the contact to be formed over the active portion of the gate, eliminating the need for extended inactive portions and achieving self-aligned contact formation.
Solution Approach 2:
The invention transitions from planar contact formation to three-dimensional contact formation by creating a recessed gate structure. The gate electrode is recessed relative to the surrounding dielectric material, allowing contact structures to be formed at different vertical levels and positions, enabling direct contact over active gate portions without requiring additional lateral space.
2Productivity
If gate dimensions are reduced to increase device density, then capacity increases, but lithographic constraints become more severe and registration accuracy deteriorates
Solution Approach 1:
The gate structure is designed to be self-aligned with the contact structure through the recessed configuration. The gate electrode itself defines the contact position, eliminating the need for separate lithographic alignment steps that become problematic at reduced dimensions. This self-aligned approach maintains registration accuracy even as device density increases.
Solution Approach 2:
The gate electrode is recessed in advance before contact formation, creating a pre-defined contact target. This preliminary structuring of the gate with exposed electrode regions allows subsequent contact formation to be precisely positioned without requiring high-precision lithographic alignment, thus maintaining manufacturing precision at reduced device dimensions.
3Reliability
If separate gate contact layers are used to ensure proper contact formation, then contact reliability improves, but device complexity and manufacturing steps increase
Solution Approach 1:
The gate structure and contact structure are merged into a single integrated structure. The recessed gate electrode serves dual functions: as the active gate element and as the contact target. This eliminates the need for separate gate contact layers while maintaining contact reliability through direct electrical connection between the interconnect and gate electrode.
Solution Approach 2:
The recessed gate electrode structure performs multiple functions simultaneously: it acts as the active gate controlling the transistor channel and as the contact target for electrical connection. This multi-functional design eliminates redundant structures and reduces overall device complexity while ensuring reliable contact formation.
Data Source
Figure 1A~2A
Figure 1B~2B
Figure 1C~2C
AI summary
Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.