Recessed Gate Structure to Eliminate Transistor Corner Effect
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Solution Overview
Problem
Transistor devices with shallow trench isolation structures face a 'corner effect' issue due to non-uniform doping concentrations at the interface region, leading to a double-hump drain current versus gate voltage (IDVG) curve, which reduces device threshold voltage and increases noise.
Innovation Solution
A recessed gate structure is implemented, where the gate is cut off at the interface region by forming recess regions on either side, preventing carrier transfer and thus disabling the corner device, thereby reducing or eliminating the double-hump IDVG curve without requiring additional masking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used, then the device can be manufactured with standard processes, but corner effect occurs leading to double-hump IDVG curve and reduced threshold voltage stability
Solution Approach 1:
The gate structure is segmented into three distinct regions: a first gate region, a recess region, and a second gate region. This segmentation allows the gate to selectively cover or expose interface regions, thereby controlling carrier transfer paths and eliminating the corner effect that causes double-hump IDVG curves, while maintaining threshold voltage stability.
Solution Approach 2:
The recess region creates local structural variation where the gate is intentionally removed or reduced over the interface region. This local modification prevents corner effect at specific locations without affecting the overall device performance, allowing stable threshold voltage while eliminating the double-hump characteristic.
2Reliability
If additional masking processes are used to address corner effect, then threshold voltage stability can be maintained, but processing complexity and cost increase
Solution Approach 1:
The recess region is formed as part of the gate structure fabrication process itself, rather than requiring subsequent masking and etching steps. This preliminary action integrates the corner effect mitigation into the standard gate formation flow, maintaining threshold voltage stability without adding processing complexity or cost.
3Object-generated harmful factors
If the gate structure is modified to eliminate corner effect, then double-hump IDVG curve is reduced, but device structure becomes more complex
Solution Approach 1:
The gate structure modification extends into the lateral dimension by creating recess regions that span across the interface region. This dimensional approach effectively eliminates carrier transfer paths responsible for the double-hump IDVG curve while integrating seamlessly with standard gate fabrication processes.
Data Source
AI summary
A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.