Recessed Gate Dielectric Layout for High-Voltage IC Breakdown Control
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Solution Overview
Problem
In mixed-signal integrated circuit (IC) devices, the use of a thick gate oxide for high-voltage circuitry can lead to a reduced M1-to-gate breakdown voltage, especially in advanced technology nodes with thin interlayer dielectric structures, resulting in undesirable bimodal subcritical drain current versus gate voltage characteristics.
Innovation Solution
The implementation of an etched recessed gate dielectric region, where a thick gate dielectric is formed and then etched to create a recessed region, avoids thinning in the corner regions and maintains a sufficient gate oxide breakdown voltage, thereby preventing bimodal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If advanced technology nodes with thin interlayer dielectric structures are used, then device scaling is improved, but M1-to-gate breakdown voltage is reduced
Solution Approach 1:
The recessed region structure utilizes the vertical dimension to provide additional spacing between the gate and M1 interconnect. This vertical separation compensates for the reduced horizontal spacing in advanced technology nodes, maintaining adequate M1-to-gate breakdown voltage while enabling continued device scaling.
Solution Approach 2:
The patent applies local quality by creating a recessed region specifically at the gate area where M1-to-gate spacing is critical. This localized structural modification provides enhanced spacing where needed without affecting the overall scaling benefits of thin interlayer dielectric structures in other regions of the device.
Data Source
AI summary
Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.