Recessed Gate Semiconductor Device for Increased Drain Current
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Solution Overview
Problem
Semiconductor devices with recesses in the main surface of the substrate face challenges in miniaturization due to insufficient drain current, which affects the stability and efficiency of the device characteristics.
Innovation Solution
A semiconductor device design where a recess is formed in the main surface extending from the contact region between the source and gate electrode layer to the contact region between the drain, allowing the side surface of the recess to act as a path for drain current, thereby increasing the drain current and enabling miniaturization without deteriorating the device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a fine trench (recess) is formed orthogonal to the channel width direction to increase effective channel width, then the MOS transistor can be miniaturized in the channel width direction while keeping stable operation characteristics, but the drain current becomes insufficient
Solution Approach 1:
The recess structure extends vertically into the substrate, utilizing the depth dimension to create additional current flow paths. By forming the recess to extend from the main surface through the channel region to the substrate, the invention transforms a two-dimensional channel width problem into a three-dimensional solution where current can flow through both the bottom wall and side surfaces of the recess, effectively increasing the current-carrying cross-section without increasing the planar footprint.
Solution Approach 2:
The recess structure divides the channel region into multiple current flow paths: current can flow through the bottom wall of the recess and through the side surfaces. This segmentation of the current path allows the device to achieve higher effective channel width while maintaining a compact overall size, as the single recess structure creates multiple parallel conduction channels.
2Reliability
If the recess depth is increased to enhance drain current through side surface conduction, then more current path is available, but the manufacturing precision becomes more difficult to control
Solution Approach 1:
The gate electrode layer serves as an intermediary reference structure that defines the recess depth. By forming the recess to extend to a predetermined depth that allows the gate electrode layer to be formed over it, the invention uses the gate structure itself as a depth marker, ensuring consistent recess depth across different devices while maintaining precise control during manufacturing.
3Area of moving object
If the recess extends through the channel region to increase effective channel width, then device miniaturization is enabled, but the channel length control becomes more challenging
Solution Approach 1:
The recess is formed with specific local characteristics: it extends from the main surface through the channel region to a predetermined depth, creating localized current flow enhancement in the channel region while maintaining normal substrate structure elsewhere. This localized modification allows effective channel width increase without affecting overall channel length control, as the recess is confined to specific regions between source and drain.
Data Source
AI summary
There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.