Recessed Gate FDSOI Transistor With SiGe Cap Layer
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Solution Overview
Problem
Fully depleted silicon-on-insulator (SOI) transistors face challenges with parasitic capacitance, area-consuming isolation, and statistical variability due to doping fluctuations, particularly in thin silicon layers, which affect electrostatic integrity and access resistance, leading to performance issues in advanced integrated circuit technologies.
Innovation Solution
The implementation of a recessed gate structure with an epitaxial SiGe and Si layer configuration, where the gate is formed in a recess defined by sidewall spacers, allowing for precise control of the Si channel thickness and incorporating a thick SiGe cap layer for enhanced strain and doping, reducing access resistance and variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin silicon layers are used in fully depleted SOI transistors, then electrostatic integrity is improved, but statistical variability due to doping fluctuations increases
Solution Approach 1:
The patent extracts the doping function from the silicon channel layer itself and relocates it to a separate doped cap layer. This allows the channel to remain undoped (improving electrostatic integrity) while still providing necessary doping in the cap layer for threshold voltage control and carrier supply.
Solution Approach 2:
The silicon structure is segmented into distinct functional layers: an undoped channel layer for electrostatic control and a doped cap layer for doping functions. This segmentation allows independent optimization of each layer's properties without compromise.
2Reliability
If doping is eliminated from the silicon layer, then threshold voltage control is improved, but access resistance increases
Solution Approach 1:
The doped cap layer acts as an intermediary between the undoped channel and the metal contacts. It provides a highly doped region that facilitates carrier transport and reduces access resistance, while the undoped channel maintains excellent electrostatic control.
3Ease of manufacture
If conventional planar structures are used, then fabrication is simplified, but electrostatic integrity deteriorates in advanced nodes
Solution Approach 1:
The patent transitions from a conventional planar structure to a vertical stacked structure with the gate wrapping around the channel in three dimensions. This enhances electrostatic control by reducing the effective channel thickness seen by the gate, while remaining compatible with standard fabrication processes.
4Reliability
If silicon layer thickness is reduced, then electrostatic control is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The doped cap layer serves as a thickness reference and etch stop layer, making it easier to control the overall structure thickness. The undoped channel thickness can be precisely controlled independently through selective etching processes using the cap layer as a mask and reference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced access resistance, improved on-current variability, and enhanced performance by controlling channel thickness and introducing compressive strain, addressing the limitations of conventional fully depleted SOI transistors.
Implementation Method 1
incorporating a thick SiGe cap layer for enhanced strain and doping, reducing access resistance and variability
Data Source
AI summary
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.