Recessed Gate FET for Low Sheet Resistance and High Density
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Solution Overview
Problem
Traditional field effect transistors (FETs) face issues with increased sheet resistance at smaller dimensions, leading to slower switching speeds and higher power consumption due to RC time delays, which are not effectively addressed in sub-32 nm processes.
Innovation Solution
A recessed metal gate FET with highly conductive source/drain extensions and a silicon germanium channel, combined with an epitaxial layer grown over a buried oxide or silicon dioxide, is used to maintain low gate electrode sheet resistance, junction depth, and junction capacitance, allowing for scalable transistor design from 50 nm to 2 nm gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional FET designs are used with smaller dimensions, then transistor density increases, but sheet resistance of the gate increases leading to slower switching speeds and higher power consumption
Solution Approach 1:
The gate electrode is recessed into the substrate below the surface level, creating a three-dimensional structure. This dimensional change allows the gate to maintain electrical connection while being positioned deeper, effectively reducing the impact of sheet resistance on switching performance while preserving high transistor density
Solution Approach 2:
The source and drain regions are made highly conductive through selective doping or material composition, creating localized high-conductivity zones. This local quality enhancement compensates for the increased gate sheet resistance by reducing overall device resistance, thereby maintaining fast switching speeds despite smaller dimensions
2Quantity of substance
If gate length is reduced to increase transistor density, then more transistors fit per chip, but RC time delays increase due to higher sheet resistance
Solution Approach 1:
By recessing the gate electrode into the substrate, the design moves from a two-dimensional surface layout to a three-dimensional structure. This allows shorter gate lengths to be implemented without proportionally increasing sheet resistance effects, as the recessed position provides better electrical contact and reduced parasitic resistance
Solution Approach 2:
The source and drain regions are modified with different material compositions or doping levels to achieve highly conductive properties. This parameter change in conductivity compensates for the increased RC time delays that would normally result from reduced gate lengths, maintaining fast switching performance
3Ease of manufacture
If traditional FET structures are used at sub-32 nm dimensions, then manufacturing continues with existing processes, but performance degrades due to increased sheet resistance and power consumption
Solution Approach 1:
The gate electrode is divided into multiple segments or layers in the recessed structure, allowing each segment to be optimized independently. This segmentation enables better control of electrical properties while maintaining compatibility with existing manufacturing processes through modular fabrication approaches
Solution Approach 2:
The source and drain regions utilize composite material structures with different compositions optimized for high conductivity. These composite materials provide the necessary electrical performance at sub-32 nm dimensions while being manufacturable with adapted existing processes, reducing power consumption without sacrificing ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of transistors with smaller footprints, lower power consumption, and increased transistor density per chip, while maintaining high switching speeds and reducing the number of process steps, thus improving the efficiency and cost-effectiveness of integrated circuit manufacturing.
Implementation Method 1
an epitaxial layer is grown over a buried oxide (BOx) or over a silicon dioxide (SiO2) layer and is used as the channel of the FET
Data Source
AI summary
A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.