Recessed Gate FET Structure for Lower Parasitic Resistance
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Solution Overview
Problem
Field effect transistors face challenges in reducing parasitic resistance and modifying electric field distribution, which degrades their large-signal RF performance, output power, gain, breakdown voltage, and bandwidth, especially in high-frequency applications like millimeter-wave 5G and 6G.
Innovation Solution
The design includes a semiconductor structure with a delta-doped layer and a specific metal contact configuration that reduces parasitic resistance and modifies the electric field distribution by inserting a delta-doped layer into the recess regions and using a graded doping profile in the wide recess layer, along with a gate metal contact formed through thermal treatment to intermix layers, thereby improving the transistor's efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal contact configuration is used, then device structure is simple, but parasitic resistance is high which degrades RF performance
Solution Approach 1:
The gate contact structure is segmented into multiple components: a first metal contact layer forming a gate electrode, a second metal contact layer forming a gate metal contact extending to the recess, and a third metal contact layer forming an upper gate metal contact. This segmentation allows optimization of each layer's function to reduce parasitic resistance while maintaining manufacturability.
Solution Approach 2:
The gate metal contact extends in multiple dimensions: horizontally along the recess to reduce contact resistance, and vertically through multiple metal layers. The upper gate metal contact provides additional vertical connectivity, creating a three-dimensional contact architecture that reduces parasitic resistance without simply increasing planar area.
2Reliability
If uniform doping is used in recess layer, then manufacturing is simple, but electric field distribution is not optimized
Solution Approach 1:
The recess layer employs non-uniform doping where the doping concentration varies with depth: higher doping concentration near the surface and lower concentration deeper in the layer. This local variation optimizes the electric field distribution to enhance breakdown voltage while maintaining a single-layer structure that is relatively simple to manufacture.
3Reliability
If gate contact is formed only at surface level, then manufacturing is simple, but gate-source and gate-drain resistance is high
Solution Approach 1:
The gate metal contact extends horizontally along the recess rather than being confined to the surface level. This extended configuration reduces the distance for charge carrier transport between gate and source/drain, thereby reducing parasitic resistance. The contact formation process integrates this extension naturally through standard photolithography and metallization steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lowers the gate-drain and gate-source resistance, enhances breakdown voltage, output power, gain, and bandwidth, and improves the efficiency of RF transistors and power amplifiers by allowing more efficient electron flow and reducing noise characteristics.
Implementation Method 1
a gate metal contact formed through thermal treatment to intermix layers
Implementation Method 2
modifying electric field distribution by inserting a delta-doped layer into the recess regions
Implementation Method 3
Electrons are injected from the Source to the Drain due to applied voltage (Vds). The electrons transit from the Ohmic metal of the Source down into the channel layer, transit along the Channel to the Drain
Data Source
AI summary
A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.