Recessed Top Metal Gate Layout for Lower-Parasitic GAA FETs
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Solution Overview
Problem
As IC devices miniaturize, the available area for forming contacts and interconnects becomes smaller, leading to increased routing complexity and parasitic resistance and capacitance, which negatively impacts manufacturing cost and performance.
Innovation Solution
A field effect transistor (FET) structure with a deeply recessed top metal gate is introduced, featuring a vertical metal gate structure with high-K dielectric material between stacked horizontal channels, vertical spacer layers, and a low-K dielectric structure above, reducing parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IC devices are miniaturized to advance computing power, then computing power increases, but routing complexity and parasitic resistance and capacitance increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked channel structures. Multiple channels are stacked vertically to increase the effective channel width and drive current capability within the same footprint, thereby advancing computing power without proportionally increasing routing complexity. The gate structure wraps around all surfaces of each channel, providing superior electrostatic control in the vertical dimension.
Solution Approach 2:
The gate structure is designed to wrap around and surround each vertical channel completely, with the gate enveloping the channel in a nested configuration. This gate-all-around structure provides comprehensive electrostatic control of the channel while maintaining a compact footprint. The high-K dielectric material is positioned between the gate and channel to enhance the electric field effect.
2Area of moving object
If IC devices are miniaturized, then component size decreases, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent employs high-K dielectric material between the gate and channel to increase the capacitance density, allowing for lower operating voltages and reduced power consumption. The vertically-stacked channel structure increases the effective channel area without increasing the device footprint, thereby reducing current density and associated parasitic effects. The deeply recessed gate structure optimizes the electric field distribution to minimize parasitic capacitance.
Solution Approach 2:
The transistor structure utilizes composite material stacking including semiconductor channels, high-K dielectric materials, and metal gate materials. This composite approach allows optimization of each layer's properties to reduce parasitic effects while maintaining compact dimensions. The combination of vertically-stacked channels with gate-all-around structures creates a composite device that minimizes parasitic resistance and capacitance.
3Area of moving object
If vertically-stacked channels are implemented, then channel width increases, but gate structure complexity increases
Solution Approach 1:
Instead of increasing channel width in the planar direction, the patent stacks multiple channels vertically in the third dimension. This allows the effective channel width to increase while maintaining a compact lateral footprint. The gate structure wraps around each channel in the vertical dimension, providing comprehensive control without requiring complex lateral extensions.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it provides electrostatic control of the channel, acts as a barrier to short-channel effects, and enables high capacitance density through the high-K dielectric. This universal structure handles multiple design requirements with a single configuration, reducing overall device complexity despite the vertically-stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deeply recessed top metal gate structure reduces parasitic capacitance and contact resistance, improving yield and reducing standard cell delay and power consumption while being cost-effective with existing tools and materials.
Implementation Method 1
The deeply recessed top metal gate structure reduces parasitic capacitance and contact resistance
Implementation Method 2
The deeply recessed top metal gate structure reduces parasitic capacitance and contact resistance
Data Source
AI summary
A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a vertical metal gate disposed between a first and second source/drain (S/D) epitaxial (EPI) structure and having a set of vertically-stacked, horizontal channels connecting the first and second S/D EPI structures through the vertical metal gate, where a top-most portion of the vertical metal gate is above a top-most channel. A high-K dielectric material is disposed between the vertical metal gate and each of the horizontal channels, and vertical spacer layers separate the vertical metal gate from the S/D EPI structures. A low-K dielectric structure is disposed above the top-most portion of the vertical metal gate and fills a recess above the vertical metal gate and between the first vertical spacer layer and the second vertical spacer layer.