Recessed Gate Memory Cell Halogen Doping Leakage
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Solution Overview
Problem
Current DRAM cells with recessed gates suffer from defects in the gate dielectric layer due to dangling bonds, leading to current leakage and reduced data retention time, which affects their performance and reliability.
Innovation Solution
A memory cell with a recessed gate structure that includes a halogen-doped dielectric layer, specifically a fluorine-containing layer, is used to reduce defects by bonding with dangling bonds, thereby minimizing current leakage paths and enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recessed gate structure is used to increase channel length and reduce current leakage, then data retention is improved, but defects are formed in the gate dielectric layer due to dangling bonds, creating current paths that release charges
Solution Approach 1:
The patent converts the harmful effect of dangling bonds (which create current leakage paths) into a beneficial effect by intentionally introducing halogen atoms that bond with these dangling bonds. The halogen doping transforms the defective oxide layer into a functional component that passivates defects and reduces gate-induced drain leakage, thereby improving data retention while maintaining the recessed gate structure.
2Productivity
If fabrication technologies are used to create recessed gates, then memory cell performance is improved, but defects are formed in the gate dielectric layer that reduce data retention time
Solution Approach 1:
The patent changes the chemical composition parameter of the gate dielectric layer by introducing halogen atoms through doping. This parameter change transforms the physical and electrical properties of the oxide layer, enabling it to passivate dangling bonds and reduce defect-related current leakage, thereby improving manufacturing quality without sacrificing productivity.
3Reliability
If the gate dielectric layer is formed on the recessed gate, then charge storage is enabled, but dangling bonds at the oxide layer interface create current paths that reduce data retention time
Solution Approach 1:
The patent introduces halogen atoms as an intermediary substance between the gate electrode and the semiconductor substrate. These halogen-doped atoms act as a mediating layer that bonds with dangling bonds at the oxide layer interface, blocking the harmful current paths while allowing the gate dielectric layer to maintain its charge storage function, thereby extending data retention time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The halogen-doped dielectric layer effectively reduces defects and current leakage, improving the performance and reliability of DRAM devices by increasing data retention time and controlling charge flow between source and drain regions.
Implementation Method 1
A memory cell with a recessed gate structure that includes a halogen-doped dielectric layer, specifically a fluorine-containing layer, is used to reduce defects by bonding with dangling bonds
Data Source
AI summary
A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.