Recessed-Gate Normally-Off HEMT With Lower ON-State Resistance
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Solution Overview
Problem
Existing high-electron-mobility transistors (HEMTs) with recessed-gate terminals suffer from high ON-state resistance due to the conductive channel being formed primarily within the channel layer, which hinders their efficient use in high-power applications.
Innovation Solution
A normally-off transistor design featuring a gate electrode recessed through a buffer region, with a resistive region in the buffer region to hinder current flow below a threshold voltage and a conductive path above it, optimizing the trade-off between threshold voltage and ON-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the conductive channel is formed primarily within the channel layer using a recessed-gate terminal, then a high breakdown threshold is achieved, but the ON-state resistance becomes high
Solution Approach 1:
The gate electrode is extended in the vertical dimension by making it recessed into the semiconductor body to a depth that reaches or exceeds the maximum depth of the resistive region. This dimensional change allows the gate to effectively control the conductive path through the buffer region, enabling low ON-state resistance while maintaining the high breakdown threshold provided by the channel layer structure.
Solution Approach 2:
The patent creates different functional regions with distinct properties: a resistive region in the buffer region that hinders current flow when the transistor is off, and a conductive path that forms when the transistor is on. The gate electrode is specifically positioned to control the transition between these local regions, achieving both high threshold voltage and low ON-state resistance through localized functional differentiation.
2Ease of operation
If a recessed-gate terminal is used to achieve normally-off operation, then a high turn-on threshold voltage is obtained, but the ON-state resistance increases
Solution Approach 1:
The patent changes the physical parameters of the gate electrode, specifically its depth of recess into the semiconductor body. By adjusting the gate depth to reach or exceed the maximum depth of the resistive region, the electrical parameters of the transistor are optimized: the threshold voltage remains high for normally-off operation, while the ON-state resistance is reduced through improved control of the conductive path in the buffer region.
3Reliability
If the gate electrode extends deeper into the semiconductor body, then control over the conductive path is improved, but the manufacturing complexity increases
Solution Approach 1:
The semiconductor body is segmented into distinct functional regions: a buffer region containing a resistive region, and a heterostructure with a channel layer. The gate electrode is selectively positioned to extend into the buffer region to a specific depth, creating a segmented structure that simplifies the control mechanism while maintaining effective control over the conductive path through the buffer region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a significant reduction in ON-state resistance while maintaining a high threshold voltage, enhancing the transistor's performance in high-power applications.
Implementation Method 1
When, in use, the voltage applied to the gate terminal generates a charge-carrier inversion in the channel layer, a conductive channel is set up in the channel layer
Implementation Method 2
The active area in the buffer region houses a resistive region configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than a threshold voltage, the electric current flow between the first and second working electrodes
Data Source
AI summary
A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.