Recessed Gate High Voltage Semiconductor Device Planarization
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Solution Overview
Problem
Conventional LDMOS transistor devices face manufacturing challenges due to the need for a thicker gate oxide layer, which leads to increased gate structure height differences with other semiconductor devices, affecting planarization processes and yield, especially during CMP, and influencing electrical characteristics.
Innovation Solution
A recess is formed in the semiconductor substrate to position the gate dielectric layer and main gate structure lower than the isolation structures, allowing for a thinner gate dielectric layer and reducing height differences, thereby simplifying manufacturing and enhancing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate oxide layer is used for high voltage requirements, then breakdown voltage is improved, but gate structure height difference with other devices increases affecting planarization and yield
Solution Approach 1:
The patent introduces a recess structure in the semiconductor substrate to create a depth dimension. The gate oxide layer and gate electrode are formed within this recess, allowing the gate structure to be positioned lower than the isolation structure top surface. This dimensional change enables the gate oxide to be sufficiently thick for high voltage operation while keeping the gate structure height difference within acceptable limits for planarization processes.
2Reliability
If gate oxide layer thickness is increased for electrical requirements, then high voltage capability is improved, but manufacturing complexity increases due to planarization issues
Solution Approach 1:
The recess structure is formed in the semiconductor substrate before depositing the gate oxide layer and gate electrode. This preliminary action creates a pre-defined depth region that accommodates the thick gate oxide structure, ensuring that the gate structure height difference is controlled from the outset rather than requiring complex post-processing planarization steps.
3Manufacturing precision
If gate structure height difference is reduced for better planarization, then manufacturing yield is improved, but gate oxide thickness may be insufficient for high voltage requirements
Solution Approach 1:
By utilizing the vertical depth dimension through the recess structure, the patent decouples the relationship between gate oxide thickness and gate structure height difference. The gate oxide can extend deeply into the recess to achieve the required thickness for high voltage operation, while the gate structure top surface remains at an appropriate height relative to isolation structures for successful planarization.
Data Source
AI summary
A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.