Recessed Gate Electrode Structure for Uniform HV-LV MOS Integration
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Solution Overview
Problem
The integration of high voltage (HV) MOS devices with low voltage (LV) MOS devices in integrated circuits is challenging due to the increased height of HV MOS devices, which complicates the manufacturing process and can lead to difficulties in achieving uniform electrical properties.
Innovation Solution
A method for forming a semiconductor device with a recessed gate electrode that has high thickness uniformity, involving the formation of a recess over a substrate, deposition of a gate dielectric layer and a multilayer film comprising a gate electrode layer and sacrificial layers, followed by planarization and etching to create a recessed gate electrode protected by sacrificial layers, ensuring uniformity and flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer thickness is increased for HV MOS devices, then the breakdown voltage is improved, but the device height increases making integration with LV MOS devices difficult
Solution Approach 1:
The patent applies local quality by creating a recessed gate electrode structure where the gate electrode is positioned at different heights in different regions. The central portion of the gate electrode is recessed deeper than the peripheral portions, allowing the gate dielectric layer to have varying thicknesses - thicker in the center for HV devices and thinner at periphery for LV devices. This enables both HV and LV MOS devices to coexist on the same substrate with uniform top surface.
2Reliability
If the gate electrode height is increased for HV MOS devices, then the breakdown voltage is improved, but the manufacturing process uniformity deteriorates
Solution Approach 1:
The patent applies preliminary action by forming a recess structure in the substrate before depositing the gate dielectric layer and gate electrode. This pre-formed recess allows subsequent deposition processes to create a gate electrode with non-uniform height profile in a single continuous process, ensuring uniform thickness control throughout the manufacturing process while achieving the required breakdown voltage for HV devices.
Solution Approach 2:
The gate electrode structure features local quality variations with different heights in different regions - the central portion is recessed deeper than peripheral portions. This enables the gate dielectric layer to have optimized thickness locally - thicker under the central region for HV breakdown voltage requirements and thinner at peripheral regions for LV device requirements - while maintaining uniform manufacturing processes.
3Device complexity
If the gate electrode is recessed into the substrate, then the device height is reduced for better integration, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of the recessed gate electrode structure with the standard CMOS fabrication process flow. The recess is formed using standard photolithography and etching techniques, and the gate dielectric and electrode materials are deposited using conventional CVD or PVD processes. This integration of the recessed structure formation into existing manufacturing processes minimizes additional process steps while achieving uniform top surface for both HV and LV devices.
Data Source
AI summary
Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.